JPS62145875A - Protecting diode for compound semiconductor device - Google Patents
Protecting diode for compound semiconductor deviceInfo
- Publication number
- JPS62145875A JPS62145875A JP28832385A JP28832385A JPS62145875A JP S62145875 A JPS62145875 A JP S62145875A JP 28832385 A JP28832385 A JP 28832385A JP 28832385 A JP28832385 A JP 28832385A JP S62145875 A JPS62145875 A JP S62145875A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion region
- compound semiconductor
- diffused
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は、化合物半導体装置の耐サージ性を高めるため
に、化合物半導体装置と一緒に形成する保護ダイオード
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a protection diode formed together with a compound semiconductor device in order to improve the surge resistance of the compound semiconductor device.
(ロ)従来の技術
化合物半導体装置、例えばガリウムーヒ素電界効果トラ
ンジスタ(以下GaAsM E S F E Tという
。)は、低雑音、高利得など優れた特性をもつマイクロ
波帯増幅素子として実用化が盛んにすすめられている。(b) Conventional technology Compound semiconductor devices, such as gallium-arsenide field effect transistors (hereinafter referred to as GaAsMESFETs), are being put into practical use as microwave band amplification elements with excellent characteristics such as low noise and high gain. is recommended.
しかしながら、GaAsMESFETはゲートがショッ
トキ接合のためゲート・ソース間、ゲート・ドレイン間
にサージエネルギが加わった場合に、ショットキ接合が
破壊されやすい。従って最近ではGaAsを用いてGa
AsMESFETと保護ダイオードをモノリシック集積
化するなどの対策がなされている。(例えば信学技報5
SD82−132.75頁乃至79頁が詳しい。)。However, since the gate of a GaAs MESFET is a Schottky junction, the Schottky junction is easily destroyed when surge energy is applied between the gate and source or between the gate and drain. Therefore, recently, GaAs has been used to
Countermeasures have been taken, such as monolithically integrating AsMESFETs and protection diodes. (For example, IEICE Technical Report 5
SD82-132. Pages 75 to 79 are detailed. ).
ところで前述した保護ダイオードとしては第3図は示す
ものがあり、GaAs基板(32〉にイオン注入等で形
成されたN型の拡散領域(33)と、前記N型の拡散領
域(33)の一部と接合するように形成されたP”型の
拡散領域(34)とにより構成され、GaAsMESF
ETのゲート・ソース間に接続された形でモノリシック
集積化されていた。By the way, the above-mentioned protection diode is shown in FIG. 3, which includes an N-type diffusion region (33) formed in a GaAs substrate (32) by ion implantation, etc., and one of the N-type diffusion regions (33). A P” type diffusion region (34) formed to connect with the GaAsMESF
It was monolithically integrated, connected between the gate and source of the ET.
(ハ)発明が解決しようとする問題点
衛士の如き構成の保護ダ・イオード(31)に於いて、
P”N接合のうちP′″の拡散領域(34)の底面の一
部とN型の拡散領域(33)で形成されている部分の面
積が大きいために寄生容量が増加し雑音指数(NF)を
大幅に劣化させる原因となっていた。(c) Problems to be solved by the invention In the protection diode (31) with a guard-like configuration,
Since the area of the part of the P''N junction formed by the bottom surface of the P'' diffusion region (34) and the N type diffusion region (33) is large, the parasitic capacitance increases and the noise figure (NF ) was causing significant deterioration.
(ニ)問題点を解決するための手段
本発明は上述した問題点に鑑みてなされ、化合物半導体
基板(2)に形成される化合物半導体装置の保護ダイオ
ード(1)に於いて、前記半導体基板(2)に形成され
る複数の一導電型の第1の拡散領域(3)と、該第1の
拡散領域(3)(3)間に接合きれる逆導電型の第2の
拡散領域(4)とを備え、前記第2の拡散領域(4)を
前記第1の拡散領域(3)より濃度を薄く深さを深く拡
散し、第1の拡散領域(3)の表面にそれぞれ設けられ
た電極間に印加していったとき第2の拡散領域(4)に
空乏層が広がり、バンチスルーすることにより降伏する
ことで解決するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a protection diode (1) for a compound semiconductor device formed on a compound semiconductor substrate (2). A plurality of first diffusion regions (3) of one conductivity type formed in 2) and a second diffusion region (4) of an opposite conductivity type that can be bonded between the first diffusion regions (3) (3). The second diffusion region (4) is diffused to a lower concentration and deeper than the first diffusion region (3), and an electrode provided on the surface of the first diffusion region (3), respectively. The solution is that when the voltage is applied between the two, a depletion layer spreads in the second diffusion region (4), and breakdown occurs due to bunch-through.
(*)作用
前記第2の拡散領域(4)を前記第1の拡散領域(3)
より深く拡散すると、第1の拡散領域(3)(3)間の
不純物濃度はほぼ均一となり、第1図に示す空乏層(5
)(点線)の様に均一に広がってゆく。(*) Effect of the second diffusion region (4) on the first diffusion region (3)
When the impurity is diffused deeper, the impurity concentration between the first diffusion regions (3) (3) becomes almost uniform, resulting in a depletion layer (5) as shown in FIG.
) (dotted line).
(へ)実施例 以下に本発明の実施例を図面を参照しながら説明する。(f) Example Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明による保護ダイオード(1)の一実施例
であり、第2図に示した如<GaASデュアルゲートM
ESFETのゲート1(GI)に接続された保護ダイオ
ード(21)の断面図を示すものである。FIG. 1 shows an embodiment of the protection diode (1) according to the present invention, and as shown in FIG.
It shows a cross-sectional view of the protection diode (21) connected to the gate 1 (GI) of the ESFET.
第1図に示す如く、少なくとも化合物半導体基板(2)
例えば半絶縁性GaAs基板に形成される2つの高不純
物濃度の一導電型(P型)の第1の拡散領域(3)があ
る。As shown in FIG. 1, at least a compound semiconductor substrate (2)
For example, there are two first diffusion regions (3) of one conductivity type (P type) with high impurity concentration formed in a semi-insulating GaAs substrate.
ここではGaAs基板(2)上に例えばCVD法等を用
いてシリコン酸化膜(6)を約5ooo人被覆し、P型
の第1の拡散領域(3)に対応するシリコン酸化膜(6
)を開口し亜鉛イオン(Z、”)をドーズ量1 X 1
0 ”cm−”、加速電圧100KeV(7)条件でイ
オン注入し、2つのP型の第1の拡散領域(3)(3)
となる0次に前記−導電型の第1の拡散領域(3)(3
)の一部と接合する逆導電型の第2の拡散領域(4)(
N型の拡散領域)がある。Here, the GaAs substrate (2) is coated with about 5000 silicon oxide film (6) by using, for example, CVD method, and the silicon oxide film (6) corresponding to the P-type first diffusion region (3) is coated.
) is opened and zinc ions (Z, ”) are added at a dose of 1 x 1
Ion implantation was performed under the conditions of 0 "cm-" and acceleration voltage of 100 KeV (7), and two P-type first diffusion regions (3) (3)
The - conductivity type first diffusion region (3) (3
) A second diffusion region (4) of the opposite conductivity type that joins with a part of (
There is an N-type diffusion region).
従って2つの前記P型の第1の拡散領域(3)(3)と
前記N型の第2の拡散領域(4)とで第2図におけるゲ
ート1(GI)に接続された2つのダイオード(1)が
PNP型で形成されゲートの保護ダイオード(1)とし
て構成される
本発明の特徴とするところは、前記第2の拡散領域(4
)を前記第1の拡散領域(3)より濃度を薄く深さを深
く拡散し、第1の拡散領域(3)2つの表面にそれぞれ
設けられた電極間にバイアスを印加していったとき第2
の拡散領域(4)に空乏層が広がりバンチスルーするこ
とにある。Therefore, the two P-type first diffusion regions (3) (3) and the N-type second diffusion region (4) form two diodes ( The feature of the present invention is that the second diffusion region (4) is formed of a PNP type and is configured as a gate protection diode (1).
) is diffused to a lower concentration and deeper than the first diffusion region (3), and a bias is applied between the electrodes provided on the two surfaces of the first diffusion region (3). 2
The reason is that the depletion layer spreads and bunches through the diffusion region (4).
つまりここでは前記GaAs基板(2)上に同様にシリ
コン酸化膜(6)を被覆し直し、前記N型の第2の拡散
領域(4)に対応する領域のシリコン酸化膜(6)を除
去し、開口部に、ドーズ量lXl0”cI[”、加速電
圧360KeVの条件でイオン注入する。また前記第1
の拡散領域(3)(3)間の不純物濃度はほぼ均一とな
り、第1図に示す空乏層(5)(点線)の様に縦に均一
に広がってゆく。That is, here, the silicon oxide film (6) is again coated on the GaAs substrate (2) in the same way, and the silicon oxide film (6) in the region corresponding to the N-type second diffusion region (4) is removed. , ions are implanted into the opening under conditions of a dose of lXl0''cI['' and an acceleration voltage of 360 KeV. Also, the first
The impurity concentration between the diffusion regions (3) (3) becomes almost uniform, and the impurity concentration spreads uniformly vertically like the depletion layer (5) (dotted line) shown in FIG.
(ト)発明の効果
本発明は以上の説明からも明らかな如く、前記第2の拡
散領域(4)を前記第1の拡散領域(3)より深く拡散
することで、空乏層(5)は一方の第1の拡散領域(3
)より他方の第1の拡散領域(3)まで縦に均一に広が
ってゆく。(G) Effects of the Invention As is clear from the above description, the present invention is capable of forming a depletion layer (5) by diffusing the second diffusion region (4) deeper than the first diffusion region (3). One first diffusion region (3
) and spreads uniformly vertically to the other first diffusion region (3).
従って、空乏層(5)の広がり方は縦に均一となるため
耐圧を精度よく制御できるようになる。Therefore, since the depletion layer (5) spreads vertically uniformly, the withstand voltage can be controlled with high accuracy.
第1図は本発明の一実施例である保護ダイオードの断面
図、第2図はデュアル・ゲートMESFETに保護ダイ
オードを設けた時の接続図、第3図は従来の保護ダイオ
ードの断面図である。
(1)は化合物半導体装置の保護ダイオード、(2)は
GaAs基板、(3)は第1の拡散領域、(4)は第2
の拡散領域、(5)は空乏層である。
第1図
第2図
第3図Fig. 1 is a cross-sectional view of a protection diode that is an embodiment of the present invention, Fig. 2 is a connection diagram when a protection diode is provided in a dual-gate MESFET, and Fig. 3 is a cross-sectional view of a conventional protection diode. . (1) is a protection diode of a compound semiconductor device, (2) is a GaAs substrate, (3) is a first diffusion region, and (4) is a second diffusion region.
The diffusion region (5) is a depletion layer. Figure 1 Figure 2 Figure 3
Claims (1)
の保護ダイオードに於いて、前記半導体基板に形成され
る複数の一導電型の第1の拡散領域と、該第1の拡散領
域間に接合される逆導電型の第2の拡散領域とを備え、
前記第2の拡散領域を前記第1の拡散領域より濃度を薄
く深さを深く拡散し、第1の拡散領域の表面にそれぞれ
設けられた電極間にバイアスを印加していったとき第2
の拡散領域に空乏層が広がり、パンチスルーすることに
より降伏することを特徴とした化合物半導体装置の保護
ダイオード。(1) In a protection diode for a compound semiconductor device formed on a compound semiconductor substrate, a plurality of first diffusion regions of one conductivity type formed on the semiconductor substrate and a junction between the first diffusion regions are provided. a second diffusion region of opposite conductivity type,
When the second diffusion region is diffused to a lower concentration and deeper than the first diffusion region, and a bias is applied between the electrodes provided on the surface of the first diffusion region, the second diffusion region
A protection diode for a compound semiconductor device characterized by breakdown due to expansion of a depletion layer in the diffusion region and punch-through.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28832385A JPS62145875A (en) | 1985-12-20 | 1985-12-20 | Protecting diode for compound semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28832385A JPS62145875A (en) | 1985-12-20 | 1985-12-20 | Protecting diode for compound semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62145875A true JPS62145875A (en) | 1987-06-29 |
Family
ID=17728691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28832385A Pending JPS62145875A (en) | 1985-12-20 | 1985-12-20 | Protecting diode for compound semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62145875A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060045A (en) * | 2001-06-07 | 2003-02-28 | Sony Corp | Semiconductor device including protection diode and method of fabricating the same |
-
1985
- 1985-12-20 JP JP28832385A patent/JPS62145875A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060045A (en) * | 2001-06-07 | 2003-02-28 | Sony Corp | Semiconductor device including protection diode and method of fabricating the same |
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