JPS6214525A - Analog and digital measuring instrument - Google Patents

Abstract

PURPOSE:To match accurately timings of both signal systems to each other by providing a sampler which samples the analog signal and a test head which introduces the analog signal and the digital signal. CONSTITUTION:In case of correction between the first analog signal source AS1 and a digital signal source DS, switches S1 and S3 are closed, and the signal source AS1 is connected to the first channel of a sampler SP, and one of outputs of the signal source DS is connected to the second channel. The signal source AS1 and the signal source DS generate the same waveform thereby, and waveforms sampled by the first and the second channels of the sampler SP are compared with each other. The phase difference between both waveforms is obtained to obtain the extent of delay of a variable delay 121 required for matching timings of the signal source DS and the signal source AS1 to each other. The sampler and switches used in the side of a test head 35 for measurement of the analog signal are used to observe the digital signal, thereby correcting accurately time bases of analog and digital signal systems.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is suitable for measuring systems in which both analog and digital signals are mixed, and is particularly suitable for setting the timing and phase of analog and digital signals to a desired relationship. The present invention relates to an analog/digital measurement device having a configuration suitable for the following.

[Prior art and its problems]

When measuring the characteristics of a semiconductor integrated circuit (IC), I
A signal is applied to C, and the signal output from the IC is thereby measured. Therefore, especially when measuring the dynamic characteristics of an IC, it is necessary to set the phases and timings between various signals applied to and output from the IC to have a known relationship. In other words, the same point in time on each terminal of the IC must be known to the measuring device.

When measuring the characteristics of an IC, such as a digital-to-analog converter, in which both digital and analog signals coexist, it is impossible to satisfactorily measure IC percentage unless the relationship between the timings of these signals is known. For example, when measuring the characteristics of a digital-to-analog converter IC, the second
The digital signals 21 and 23 shown in FIG. 2(a) are applied to the ICIC from the measuring device, and the converted analog signal 25 shown in FIG. 2(b) K is measured by the measuring device. Here, what we want to ultimately measure is I as shown in Figure 2 (c).
There is often a time relationship between the input (digital signals 21 and 23) and the output (analog signal 25) at the terminal of C (where the lead wire of the chip is attached, the bin of the pan cage, etc.). At this time, it is necessary to calibrate the digital signal time axis 2 old in the digital signal system and the analog signal time axis 203 in the analog signal system, and position the signals of both systems on the time axis 205 near the terminal of the IC.

In conventional IC measurement devices, accurate calibration between the digital and analog support axes is extremely difficult or impossible. That is, conventionally, the only way to do this was to manually adjust the phase relationship while checking the phase relationship between the two systems using a time interval meter using a counter or a sampling scope. However, as shown in FIG. 3, an actual IC measuring device is separated into a measuring section 31 that generates and measures signals and a test head 35 that electrically and mechanically contacts the IC 37. They are connected by a cable 33 for signal transmission that reaches several meters in length. Measurements using a time interval meter or sampling scope for calibration can only be performed on the measuring section 31 side. As the frequency of the signal to be calibrated increases,
Calibration errors due to the skew of the cable 33 become large. This effectively precludes meaningful calibration when attempting to perform measurements on, for example, video analog-to-digital converters or digital-to-analog converters.

[Purpose of the invention]

An object of the present invention is to accurately calibrate the timing between the time axes of both an analog signal system and a digital signal system.

[Overview of the invention]

According to a preferred embodiment of the invention, the test head is provided with a sampler that samples the analog measurement signal at the timing of a given clock.

This sampler samples the analog signal generated by the measurement target and sends it to the measurement unit via a cable. A switch is provided in the test head for introducing the signal. With this configuration, both analog and digital signals applied to the measurement target can be sampled near the measurement target, so the timing of both signal systems can be matched extremely accurately.

[Explanation of Examples]

FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, an IC 37 to be measured (FIG. A first analog signal source As includes an analog signal generator 103 that generates analog signals of various patterns based on a clock given to the clock; and generates analog signals of various patterns based on a clock given via a variable delay 105; A second analog signal source As2 is provided, which includes an analog signal generator 107 for generating a signal.The analog signal obtained from the IC in the test head 35 is applied to the first channel and the second channel of the sampler Sp. This analog signal is sampled by a clock given from the variable delay 111 of the measuring section 31, and the voltage obtained by this sampling is held, and the 17th log measuring section Aml and the second analog measuring section Am2 in the measuring section 31 The first analog measuring section Am
1 and the second analog measuring section "m2, the sampler Sp
The output is digitized using a DC (analog-to-digital converter). This digitized output is further subjected to various types of processing and analysis, but since this point is not directly related to the gist of the present application, a description thereof will be omitted.

Further, in the digital signal source, a digital signal generator 123 is provided which generates an n-pin digital signal based on a tarlock applied via a variable delay 121. Furthermore, the digital measurement section Dm is provided with a digital pattern analyzer 133 that latches and analyzes the n-bit digital signal obtained from the IC 37 (FIG. 3) to be measured using a clock given from a variable delay 131. It is being A signal from the common clock generator 11 is directly transmitted to each part in the measuring section 31.
Alternatively, each part can operate synchronously since it is provided via the timing generators 13 and 15.

The embodiment of the invention shown in FIG. 1 further includes a switch Sre Stv 83 within the test head 35.
tS4 is provided so that the timing and phase relationship between the digital signal system and the analog signal system can be calibrated.

An example of calibration using these switches 81 to S4 will be shown below.

First, the first analog signal source A3I and the second analog signal source A
s! Perform calibration in the cabinet. Therefore, switches S+, S
Close Z and leave switch 83.54 open.

Here, the analog signal generators 103 and 107 each generate a suitable analog signal waveform, such as a sine wave A, .
Generate A2. By sampling these sine waves AI+2 with the 1% second channel of the sampler Sp as shown in FIG.
ifiif'5! :#A"・Ax f)*mM f/"
'11・I can do it. By setting the variable delay 105 to compensate for this phase difference θa, the calibration between the first analog signal source ASI and the second analog signal source s2 is completed. In addition, here, the 1st and 2nd
It is assumed that the characteristics of the channels are sufficiently uniform. if,
If it is necessary to calibrate the timing between both channels, for example, one analog signal may be observed simultaneously on both channels.

Furthermore, since the method of sampling the high frequency repetitive signal is not directly related to the gist of the present invention, a description thereof will be omitted.

Next, calibration, that is, timing alignment, between the first analog signal source Asl and the first analog measuring section Am1;
Do the following. In this case, close switch Sl.

An appropriate waveform, for example rectangular wave input 3 (FIG. 5), is provided from the analog signal generator 103 and sampled by the first channel of the sampler S. Sampler 5pf) The variable delay 111 that provides the sampling timing is changed so that the rectangular wave A3 generated by analog signal generator 1030 and the waveform sampled by sampler Sp are observed to be in phase.

To do this, the sampling timing may be varied, for example, by binary length, so that the sampler Sp captures the rising edge of the square wave (see Figure 5). Then, if the delay amount of the variable delay Ill is increased, waveform A4 appears to occur at an earlier timing as shown by arrow a, and conversely, if the delay amount is decreased, it appears to occur at a later timing as already shown by the arrow. Next, a calibration is performed between the first analog 1d signal source As1 and the digital signal source J)s. Therefore, the switch S+ is closed to connect the first analog signal source AsI to the first channel of the sampler Sp, and the switch S3 is closed to connect one of the outputs of the digital signal source J)scOn to the second channel. output (in addition, the digital signal source Ds
Although the skew adjustment between the outputs of the On books is a separate matter, it is not directly related to the gist of the present invention, so it will not be explained here). Then, the first analog signal source AsI and the digital signal source Ds generate the same waveform, and the waveform λ5·Dl sampled by the first and second channels of the sampler Sp is compared. As a result, the phase difference θd between both waveforms is obtained, so the first
The amount of delay of the variable delay 121 required to match the timing of the analog signal source Asl is determined. Also, the fifth
As explained in connection with the figure, the necessary delay amount of the variable delay 121 may be determined by binary search or the like.

Next, calibration is performed between the digital signal source and the digital measuring section Dm. To do this, close switch 84 and test one of the outputs of digital signal source Ds.
It is led to the digital measuring section Dm via the head 35. Then, by changing the amount of delay of the variable delay 131 and changing the timing at which the digital pattern analyzer latches the input signal, adjustment is made so as to capture the rising point of the input signal. This is similar to the timing adjustment between the first analog signal source ASI and the first analog measurement unit Aml described with reference to FIG. 5.

It should be noted that the calibration described above is merely an example, and given the present invention, other calibration flatheads and accompanying modifications of the apparatus will be apparent to those skilled in the art.

〔Effect of the invention〕

As explained above, according to the present invention, by observing digital signals using a sampler installed on the test head side for measuring high-frequency analog signals, both analog signal systems and digital signal systems can be measured. Extremely accurate calibration between time axes is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an analog/digital measuring device according to an embodiment of the present invention, and FIG. 2 is a block diagram for explaining the relationship between the time axis of the digital signal system and the time axis of the analog signal system. A timing chart, FIG. 3 is a simplified block diagram showing the configuration of an IC measuring device to which the present invention is applied, and FIGS. 4 to 6 are measurements made using an embodiment of the present invention shown in FIG. 3 is a timing chart for explaining an example of a calibration operation performed. ll: Clock generator, 31: Measurement section, 33: Cable, 35: Test head, 105.111,1
21,131: Variable delay, As+: First analog signal source, AS2: Second analog signal source, Am: First analog measuring section, Am2: Second analog measuring section, I),: Digital signal source, Dm= Digital measuring section, Sp: sampler, Sl, S2. SL, S4: Switch. Out J! Representative of Yokozutsu Heuret Backard Co., Ltd. Patent attorney Tsugu Hasegawa Figure 3

Claims (3)

[Claims] (1) A measuring section including a signal source and a measuring device, a test head section connected to the object to be measured, and a means for connecting the measuring section and the test head section, and a digital signal and an analog signal. An analog/digital measurement device that applies and measures the voltage to the measurement target, comprising a sampler means for sampling an analog signal from the measurement target at the timing of a given clock signal and sending the sample to the measurement unit; An analog/digital measuring device characterized in that the test head section is provided with switch means for introducing an applied analog signal or digital signal into the sampler means. (2) The analog/digital measuring device according to claim 1, wherein the sampling means has a plurality of sampling channels. (3) In the analog/digital measuring device according to claim 1, the test head section is provided with a switch means for returning a digital signal given from the measuring section to the measuring section. An analog/digital measuring device characterized by: