JPS62141520A - Liquid crystal driving method - Google Patents

Liquid crystal driving method

Info

Publication number
JPS62141520A
JPS62141520A JP28250085A JP28250085A JPS62141520A JP S62141520 A JPS62141520 A JP S62141520A JP 28250085 A JP28250085 A JP 28250085A JP 28250085 A JP28250085 A JP 28250085A JP S62141520 A JPS62141520 A JP S62141520A
Authority
JP
Japan
Prior art keywords
voltage
signal
liquid crystal
period
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28250085A
Other languages
Japanese (ja)
Inventor
Koji Yamagishi
山岸 浩二
Takahiro Fuse
孝弘 布施
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP28250085A priority Critical patent/JPS62141520A/en
Publication of JPS62141520A publication Critical patent/JPS62141520A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To drive liquid crystal at a low voltage by connecting two kinds of scanning electrode driving circuits which differ in reference voltage to scanning electrodes of a liquid crystal panel alternately, putting one on a plus side and the other on a minus side about a specific bias point, and eliminating DC unbalance between driving voltages by utilizing a certain period in one frame. CONSTITUTION:When a shift data signal SR for scanning is outputted from a display control circuit 5 to the 1st scanning electrode driving circuit 2 in synchronism with a vertical synchronizing signal, this shift data signal SR is shifted in a shift register 11 in synchronism with shift clocks -phiN2 and phiN2 having a period 2H and the output of a stage where the shift data signal of this shift register 11 opens a gate 14 to select a voltage VO; when there is a blanking period signal phiB, a gate 16 is closed and a gate 17 is open, so a voltage -VO/a is selected. Further, the 2nd scanning electrode driving circuit 3 selects a voltage -VO with the output of a stage where the shift data signal SR of a shift register 11' is stored, and when there is a blanking period signal phiB, a voltage VO/a is selected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、液晶駆動方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a liquid crystal driving method.

〔発明の従来技術とその間煩慮〕[Prior art to the invention and complications involved]

マドIJクス型TJM液晶を時分割駆動する場合の駆動
波形としては、第6図に示すようなものが知られている
。最適バイアス駆動法と呼ばれるもので、理論的に最大
の動作マージンを得ることができる。しかしながら、信
号′f11fi駆動波形菌の振幅はylVOlとなり(
αはバイアス比)1〜2v(ボルト)程度で済むが、走
査電極駆動回路閃の最大振幅は21V0、となって30
v以上の電圧が必要になる。そのため走査′へ啄駆劾回
路は30v以上の耐圧が必要となり、製造−ヒ困誰が伴
なう問題がある。
The drive waveform shown in FIG. 6 is known as a drive waveform for time-division driving of a Mado IJ type TJM liquid crystal. This method is called the optimal bias driving method, and it is possible to theoretically obtain the maximum operating margin. However, the amplitude of the signal 'f11fi driving waveform becomes ylVOl (
α is the bias ratio) 1 to 2 V (volt), but the maximum amplitude of the scan electrode drive circuit flash is 21V0, which is 30V.
A voltage higher than v is required. Therefore, the scanning circuit needs to have a withstand voltage of 30 V or more, which poses problems in manufacturing.

一方、第7図に示すような駆動波形も知られている。こ
の場合は、信号を極駆動波形も走査゛イ極駆動波形も最
大振幅は1Volであり、15v根度である。走査電極
駆動回路+1111は15v程度の耐圧で十分製造でき
るが、信号電極磁動回路は構成が非常に複雑であり、し
かもテレビジョン表示に使う場合は3 M Hz以上の
高速動作が要求されるので、15vの耐圧を得るには製
造上田作が伴なうという問題がある。
On the other hand, a drive waveform as shown in FIG. 7 is also known. In this case, the maximum amplitude of both the polar drive waveform and the scanning polar drive waveform of the signal is 1 Vol, and the amplitude is 15V. The scanning electrode drive circuit +1111 can be manufactured with a withstand voltage of about 15V, but the signal electrode magnetic circuit has a very complicated structure, and when used for television display, high-speed operation of 3 MHz or higher is required. , there is a problem in that obtaining a withstand voltage of 15V requires manufacturing work.

従って、従来の液晶駆動方法では、第6図の波形を採用
しても第7図の波形を採用しても、いずれにしても高度
な製造技術を必要とする問題があった。
Therefore, in the conventional liquid crystal driving method, whether the waveform shown in FIG. 6 or the waveform shown in FIG. 7 is adopted, there is a problem in that a sophisticated manufacturing technology is required.

〔発明の目的〕[Purpose of the invention]

この発明は上記事情に鑑みて成されたもので、従来の液
晶駆動方法に対し、信号電IF@駆動回路の駆動電圧を
上げずに走査1!極駆動回路の駆動電圧を下げて、どち
らの駆動回路も低い・成田で駆動することめできる液晶
駆動方法を提供することを目的とする。
This invention has been made in view of the above circumstances, and in contrast to the conventional liquid crystal driving method, it is possible to perform one scan without increasing the driving voltage of the signal electric IF@drive circuit! It is an object of the present invention to provide a liquid crystal driving method in which the driving voltage of a pole driving circuit is lowered so that both driving circuits can be driven at a low voltage.

〔発明の要点〕[Key points of the invention]

この発明はこのような目的を達成するため、基準電圧の
異なる走査電極駆動回路を2種類用いて、それぞれの出
力端子を液晶パネルの走査′ぺ極に交互に配線し、それ
ぞれの駆動回路をあるバイアス点を基準として一方を+
側、他方を一側で動作させると共に、1フレーム内の一
定期間を用いて駆動電圧の直流アンバランスを防ぐよう
にしたことを特徴とする。
In order to achieve this object, the present invention uses two types of scan electrode drive circuits with different reference voltages, and alternately wires their respective output terminals to the scan electrodes of the liquid crystal panel. + one side based on the bias point
The present invention is characterized in that one side is operated on the other side, and a certain period within one frame is used to prevent DC imbalance of the drive voltage.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照してこの発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図はこの発明の液晶駆動方法を実現するための回路
ブロック図で、1は走査’iit極120本、信号電極
160本の液晶パネル、2は第1の走査電極駆動回路、
3は第2の走査電極@動回路、4は信号電極駆動回路で
ある。第1の走査電極駆動回路2は液晶パネル1の奇数
番目の走査電極X1、×3、・・・X119に接続され
、第2の走査電極駆動回路3は液晶パネル1の偶数番目
の走査域41i×2、X4、・・・X120に接続され
ている。
FIG. 1 is a circuit block diagram for realizing the liquid crystal driving method of the present invention, in which 1 is a liquid crystal panel with 120 scanning electrodes and 160 signal electrodes, 2 is a first scanning electrode driving circuit,
3 is a second scanning electrode@driving circuit, and 4 is a signal electrode driving circuit. The first scan electrode drive circuit 2 is connected to odd-numbered scan electrodes X1, ×3, ... X2, X4, ... are connected to X120.

一方、信号電極駆動回路4は液晶パネル1の各信号″電
極Y1、Y2、・・・Y160に接続されている。
On the other hand, the signal electrode drive circuit 4 is connected to each signal electrode Y1, Y2, . . . Y160 of the liquid crystal panel 1.

また、第1の走査電極駆動回路2にはME源電圧としr
Vo、GND(グラウンド)、−−vo(αハα バイアス比)が、fJ/c2の走査電極駆動回路3には
−Vo%GND、 −TDが、そして信号電極駆動回路
4 jc ハVDn (+11E fA )、G N 
D 、 −Vo 、 −−Vo f)Sα      
     α それぞれ供給されている。5は表示制御回路で、走査側
制御信号Aをレベルシフ+6.7を介して走査電極駆動
回路2.3に供給し、信号側制御信号B婆信号電極駆動
回路4に供給する。走査側割φtミブランキング期間信
号φl゛を含み一信号側制御信号Bは表示データロ1シ
フトクロツクφ−、ラッチクロック−11階調信号作成
りロック−Cフレーム切換信号φfを含む。
Further, the first scan electrode drive circuit 2 has an ME source voltage r
Vo, GND (ground), -vo (α bias ratio), fJ/c2 scan electrode drive circuit 3 has -Vo%GND, -TD, and signal electrode drive circuit 4 jc VDn (+11E fA), GN
D, -Vo, --Vof)Sα
α are supplied respectively. Reference numeral 5 denotes a display control circuit which supplies the scanning side control signal A to the scanning electrode drive circuit 2.3 via a level shift +6.7, and supplies the signal side control signal B to the signal electrode drive circuit 4. The scanning side control signal B includes a blanking period signal φl, a display data row 1 shift clock φ-, a latch clock 11, a gradation signal creation lock C frame switching signal φf.

第2図は液晶駆動波形を示すもので、(1)は第1の走
査1極駆動回!2のXlの駆動波形、(2)は信号[事
駆動回路4のYlの駆動波形である。信号型、1駆動波
形はYlがすべて選択され′る場合を例にとっており、
1コモン期間毎に反転するようジこなっている。(3)
はXl−Ylの液晶にかかる電圧の波形である。また、
Ttはlフレーム T oは1走査心極の選択期間(1
コモン期間)、TCは直流分補正期間である。なお、第
2の走査電極駆動回路3から出力される波形はi3図に
、示すよかにグラウンドレベルGNDを基単に反転した
電位となる。1 さて、このような波形で液晶を駆動すれば、第2図から
明らかなように走査電極駆動信号の振幅ハVo +−!
−Vo、 M 号1111 t N 駆ftH1fr 
号ノ振+14jハ:TD ’t’α 〆斉ませるこ、とができるが、以下にこの波形で駆動す
る場合の各種2条件について検討してみる。
Figure 2 shows the liquid crystal driving waveform, and (1) is the first scanning single-pole driving time! (2) is the drive waveform of Yl of the signal drive circuit 4. The signal type and 1 drive waveform are based on the case where all Yl are selected.
It is arranged so that it is inverted every one common period. (3)
is the waveform of the voltage applied to the Xl-Yl liquid crystal. Also,
Tt is 1 frame T o is the selection period of 1 scanning pole (1
(common period), TC is a DC component correction period. Note that the waveform output from the second scan electrode drive circuit 3 has a potential that is inverted based on the ground level GND, as shown in Figure i3. 1 Now, if the liquid crystal is driven with such a waveform, as is clear from FIG. 2, the amplitude of the scanning electrode drive signal becomes Vo +-!
-Vo, M No. 1111 t N Drive ftH1fr
It is possible to make the signal waveform +14j c: TD 't'α 〆uniform, but below we will consider two various conditions when driving with this waveform.

■ 交、□流、・枢動条件。■ Exchange, □flow, pivot conditions.

x−yi−画素選択期間と非選択期間が等しいと仮定す
る。と、液晶印加電圧VaVは。
Assume that the x-yi-pixel selection period and non-selection period are equal. And the liquid crystal applied voltage VaV is.

Vav =、 Vo Tc −Vo TnTN液晶は一
般に直流を印加できないので、Vαν=O ;、 ’l’c = a ’l’o         
  −・= 11)ここで、上記仮定枦成立しないと考
えると、(1)式%式%: となる。120X160の液晶パネルにNTSO方式テ
方式テレビ9億2 TD = 2 H (水平走査期間) TF=2・65.5H α=11.5(後述) であるから、±TDはほぼ無視できる範囲にある。
Vav =, Vo Tc - Vo TnTN liquid crystal generally cannot be applied with direct current, so Vαν = O ;, 'l'c = a 'l'o
-・= 11) Here, if we consider that the above assumption does not hold, then formula (1) % Formula %: 120 x 160 LCD panel with NTSO system TV 900 million 2 TD = 2 H (horizontal scanning period) TF = 2 65.5 H α = 11.5 (described later), so ±TD is almost negligible. .

また、nTrの期間を考えると上記仮宝はほぼ成立する
と考えてよい。
Furthermore, considering the period of nTr, it can be considered that the above-mentioned provisional treasure is almost established.

■ 最適バイアス比条件 選択点印加電圧波形の実効値は (1)式を代入すると、 非選択点印加電圧波形の実効値は (11式を代入して、 選択点と非選択点の印加電圧比(マージン)αは、αが
大キくなる程コントラストは高くなり、αの最大条件は フα 2α である。よって、 t   ’po t (1+(α−2α)5) 鵞  TD        t   T。
■ Optimum bias ratio condition The effective value of the applied voltage waveform at the selected point is calculated by substituting equation (1), and the effective value of the applied voltage waveform at the non-selected point is (substituting equation 11, the applied voltage ratio between the selected point and non-selected point is (Margin) The larger α is, the higher the contrast is, and the maximum condition for α is α 2α.Therefore, t'pot (1+(α-2α)5) TD t T.

、°、(2z−2)(1+(z +2z)、5)=(2
z+2)(1+(cL−2a)、1=、)F ここで、5−βとおくと β=α2 β〉0であるから、 α=F(βはデユーティ比の逆数)・・・・・・(2)
従って最適バイアス比条件に合致している。
, °, (2z-2)(1+(z +2z),5)=(2
z+2) (1+(cL-2a), 1=,)F Here, if we set 5-β, then β=α2 β〉0, so α=F (β is the reciprocal of the duty ratio)...・(2)
Therefore, the optimum bias ratio condition is met.

■ TDの期間条件 TCの期間は直流アンバランスを1方ぐための期間であ
り、走査はできない。従って、走査線数をNとすると N=U TD この式に(1)、(2)式を代入すると=β−7 実施例のようにN=120とすると、 120=β−Dl 、°、β= 131.5 α=Fゴイ5=11.5 以上よりNTSOe%準方式を用いた120X160画
素の液晶表示のTD,TC,1’Fは以下のようlこな
る。
■ TD period condition The TC period is a period for correcting DC imbalance, and scanning is not possible. Therefore, if the number of scanning lines is N, then N = U TD Substituting equations (1) and (2) into this equation = β-7 If N = 120 as in the example, 120 = β-Dl, °, β=131.5 α=Fgoi5=11.5 From the above, TD, TC, and 1'F of a 120×160 pixel liquid crystal display using the NTSOe% semi-method are as follows.

TD = 2 H Tc = 22.5 H TF=262.5H 従ってTl?はテレビジョンの垂W m 線M間に近く
、テレビ画像表示方法としては好都合である。
TD = 2 H Tc = 22.5 H TF = 262.5H Therefore, Tl? is close to the vertical W m line M of the television, which is convenient as a method of displaying television images.

次に、第4図を参照して第1の走査電極主動回路2及び
第2の走査電極、駆動回路3の主要部の権威について説
明する。第4図(α)は第1の走査!啄駆動回烙2の主
要部、同図(A)はf842の走査tcq駆動回路3の
主要部を示す。11は119役シフトレジスタであり、
走査用データ信号SRを互いに位相の反転した2相シフ
トクロツタφN2、φN2でシフトする。このシフトク
ロックψN2、ψN2は水平同期信号の2倍の周期を持
つ信号である。
Next, the authority of the main parts of the first scan electrode active circuit 2, the second scan electrode, and the drive circuit 3 will be explained with reference to FIG. Figure 4 (α) is the first scan! The main part of the taku drive circuit 2, and FIG. 11 is a 119 role shift register,
The scanning data signal SR is shifted by two-phase shift clocks φN2 and φN2 whose phases are opposite to each other. These shift clocks ψN2, ψN2 are signals having a period twice that of the horizontal synchronizing signal.

12はインバータ13、ゲート14及び15から成るマ
ルチプレクサであり、シフトレジスタ11からの出力が
1″のときはゲート14が開いて信号@zlを、′O″
′のと寺はゲート15が開いて信号線lxを選択する。
12 is a multiplexer consisting of an inverter 13, gates 14 and 15, and when the output from the shift register 11 is 1'', the gate 14 is opened and the signal @zl is output as 'O''.
In the case of ', the gate 15 is opened and the signal line lx is selected.

信号@t1には成源電圧vOが接続され、信号線t2に
は′に源電圧() ND及び−−Voがゲート16.1
7を介して阪峠α されている。ゲート16はブランキング期間信号φlが
無いときにインバータ18の出力力f″′1″となって
開き、ゲート15はブランキング期間信号φ曹が11”
のときに開く。ブランキング期間信号φ論はTcに等し
い期間1″化なる信号であるウ   ゛ 第4図tb)に示す第2の走査1を横駆動回路3の構成
は、電源電圧が−Vo%GND、−■に変わり、α シフトレジスタ11′が120段ある点が違うだけで他
は同様であるので、説明は省略する。
The source voltage vO is connected to the signal @t1, and the source voltage ()ND and -Vo are connected to the signal line t2 at the gate 16.1.
7 through Saka Pass α. The gate 16 opens when the blanking period signal φl is not present, and the output power of the inverter 18 becomes f''1'', and the gate 15 opens when the blanking period signal φl is 11''.
Opens when. The blanking period signal φ is a signal whose period is 1'', which is equal to Tc. The only difference is that there are 120 stages of α shift registers 11' instead of (2), and the rest is the same, so the explanation will be omitted.

以上のように構成される回路尋ζあっては、垂直同期信
号に同期して走査用シフトデータ信号8Rが表示制御回
路5から第1の走査電極駆動回路2へ出力されると、こ
のシフトデータ信号8Rはシフトレジスタ11内を周期
2HのシフトクロックφN2、φN2に同期してシフト
し、シフトレジスタ11のシフトデータ信号が記憶され
ている段の出力がゲート14を開いて電圧Voを選択し
、他の段の出力はゲート15を開いて電圧GNDを選択
する。また、ブランキング期間信号φ烏のあるときは、
ゲート16が閉じゲート17が開くから電圧−j−Vo
が選択される。従って、第3図(1)に示すような走査
電極駆動波形が得られる。また、第2の走査電極駆動回
路3ではシフトレジスタ11 のシフトデータ信号SR
が記憶されている段の出力が電圧−Voを選択し、他の
段の出力は電圧GNDを選択し、更にブランキング期間
信号φ1のあるときは電圧−Voを選択するので、fa
3図(2)α に示すような駆動波形が得られる。
In the circuit structure configured as described above, when the scanning shift data signal 8R is output from the display control circuit 5 to the first scanning electrode drive circuit 2 in synchronization with the vertical synchronization signal, this shift data The signal 8R is shifted in the shift register 11 in synchronization with shift clocks φN2 and φN2 with a period of 2H, and the output of the stage in which the shift data signal of the shift register 11 is stored opens the gate 14 and selects the voltage Vo. The outputs of the other stages open the gate 15 and select the voltage GND. Also, when there is a blanking period signal φ,
Since gate 16 is closed and gate 17 is open, voltage -j-Vo
is selected. Therefore, a scanning electrode drive waveform as shown in FIG. 3(1) is obtained. Further, in the second scan electrode drive circuit 3, the shift data signal SR of the shift register 11 is
The output of the stage in which is stored selects the voltage -Vo, the outputs of the other stages select the voltage GND, and furthermore, when the blanking period signal φ1 is present, the voltage -Vo is selected, so fa
A drive waveform as shown in Figure 3 (2) α is obtained.

従って、走査電極駆動信号X * 、X x、X 11
9、X 110を例をことって図示するとIIES図の
ようになるO な詔、信号電極駆動回路4の構成は86図に示す従来の
駆動波形を発生する回路とほぼ同様であるので説明は省
略する。
Therefore, scanning electrode drive signals X *, X x, X 11
9. If X 110 is illustrated as an example, it will look like an IIES diagram.The configuration of the signal electrode drive circuit 4 is almost the same as the conventional drive waveform generating circuit shown in FIG. Omitted.

〔発明の効果〕 以上説明したように、この発明によれば、基準電圧の異
なる2種類の走査電極駆動回路を用いて、それぞれの出
力端子を液晶パネルの走査電極に交互に接続し、それぞ
れの駆動回路をあるバイアス点を基準として一方は+側
、他方は一側で動作させると共に、1フレーム内の一定
期間を用いて駆動電圧の直流アンバランスを防ぐように
したから、走査電極駆動回路も信号電極駆動回路も低い
電圧で駆動することができ、シ小も直流アンバランスも
起こらない効果がある。
[Effects of the Invention] As explained above, according to the present invention, two types of scan electrode drive circuits with different reference voltages are used, and their respective output terminals are alternately connected to the scan electrodes of the liquid crystal panel. Since the drive circuit is operated on one side with a certain bias point as a reference and the other side is operated on the one side, and a certain period within one frame is used to prevent DC imbalance of the drive voltage, the scan electrode drive circuit also The signal electrode drive circuit can also be driven with a low voltage, which has the effect of causing no small voltage or DC imbalance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第5図は本発明の一実施例を説明するための図
、第6図、第7図は従来技術を示す図であり、瀉1図は
本発明を実現するための回路ブロック図、@2図、第3
図、tIA5図は液晶駆動波形を示す図、p44図は走
資電!@4に動回路の主要部構成を示す図、第6図、!
lK7図は従来の液晶駆動波形を示す図である。 l・・・液晶パネル 2・・・第1の走査電極駆動回路
3・・・第2の走査電極駆動回路 4・・・信号電極駆
動回路 5・・・表示制御回路 6.7・・・レベルシ
フタ 11・・・シフトレジスタ 12・・・マルチプ
レクサ
Figures 1 to 5 are diagrams for explaining one embodiment of the present invention, Figures 6 and 7 are diagrams showing the prior art, and Figure 1 is a circuit block for realizing the present invention. Figure, @Figure 2, 3rd
Figure, tIA5 figure shows the liquid crystal drive waveform, p44 figure shows the running current! @4 is a diagram showing the configuration of the main parts of the dynamic circuit, Figure 6,!
Figure IK7 is a diagram showing a conventional liquid crystal drive waveform. l...Liquid crystal panel 2...First scan electrode drive circuit 3...Second scan electrode drive circuit 4...Signal electrode drive circuit 5...Display control circuit 6.7...Level shifter 11...Shift register 12...Multiplexer

Claims (1)

【特許請求の範囲】 液晶パネルの奇数番目の走査電極を非選択期間の駆動電
圧を基準(0)として選択期間は電圧Vで駆動すると共
に、所定の直流分補正期間は電圧−1/αV(αはバイ
アス比)で駆動し、 偶数番目の走査電極を非選択期間は電圧0、選択期間は
電圧−Vで駆動すると共に、上記直流分補正期間は電圧
(1/α)Vで駆動し、 信号電極を選択期間と非選択期間は電圧±/αV、直流
分補正期間は電圧0で駆動すると共に、選択期間と非選
択期間は1走査電極選択期間T_D毎に極性を反転し、 上記直流分補正期間をほぼa・T_Dとすることを特徴
とする液晶駆動方法。
[Scope of Claims] Odd-numbered scan electrodes of the liquid crystal panel are driven with a voltage V during the selection period with the drive voltage during the non-selection period as a reference (0), and a voltage −1/αV ( α is the bias ratio), and the even-numbered scanning electrodes are driven with a voltage of 0 during the non-selection period and with a voltage of -V during the selection period, and are driven with a voltage of (1/α)V during the DC component correction period, The signal electrode is driven with a voltage of ±/αV during the selection period and the non-selection period, and with a voltage of 0 during the DC component correction period, and the polarity of the selection period and the non-selection period is reversed every scan electrode selection period T_D. A liquid crystal driving method characterized in that a correction period is approximately a·T_D.
JP28250085A 1985-12-16 1985-12-16 Liquid crystal driving method Pending JPS62141520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28250085A JPS62141520A (en) 1985-12-16 1985-12-16 Liquid crystal driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28250085A JPS62141520A (en) 1985-12-16 1985-12-16 Liquid crystal driving method

Publications (1)

Publication Number Publication Date
JPS62141520A true JPS62141520A (en) 1987-06-25

Family

ID=17653245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28250085A Pending JPS62141520A (en) 1985-12-16 1985-12-16 Liquid crystal driving method

Country Status (1)

Country Link
JP (1) JPS62141520A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02111919A (en) * 1988-10-21 1990-04-24 Stanley Electric Co Ltd Lcd driving method
US5048934A (en) * 1988-11-01 1991-09-17 Sharp Kabushiki Kaisha Method of driving ferroelectric liquid crystal without timing conversion circuitry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02111919A (en) * 1988-10-21 1990-04-24 Stanley Electric Co Ltd Lcd driving method
US5048934A (en) * 1988-11-01 1991-09-17 Sharp Kabushiki Kaisha Method of driving ferroelectric liquid crystal without timing conversion circuitry

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