JPS6213849B2 - - Google Patents
Info
- Publication number
- JPS6213849B2 JPS6213849B2 JP2269880A JP2269880A JPS6213849B2 JP S6213849 B2 JPS6213849 B2 JP S6213849B2 JP 2269880 A JP2269880 A JP 2269880A JP 2269880 A JP2269880 A JP 2269880A JP S6213849 B2 JPS6213849 B2 JP S6213849B2
- Authority
- JP
- Japan
- Prior art keywords
- delay
- circuit
- type flip
- flops
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2269880A JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2269880A JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56120223A JPS56120223A (en) | 1981-09-21 |
| JPS6213849B2 true JPS6213849B2 (enrdf_load_stackoverflow) | 1987-03-30 |
Family
ID=12090084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2269880A Granted JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56120223A (enrdf_load_stackoverflow) |
-
1980
- 1980-02-27 JP JP2269880A patent/JPS56120223A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56120223A (en) | 1981-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3252678B2 (ja) | 同期式半導体メモリ | |
| US20080253203A1 (en) | Data output circuit for semiconductor memory apparatus | |
| JPH0480350B2 (enrdf_load_stackoverflow) | ||
| KR960006293A (ko) | 위상고정루프를 구비하는 전송시스템 및 위상고정루프 | |
| JPS6213849B2 (enrdf_load_stackoverflow) | ||
| JPS5927624A (ja) | 論理変更可能な集積回路 | |
| JP2532718B2 (ja) | 半導体集積回路装置 | |
| JP2850671B2 (ja) | 可変遅延回路 | |
| JPS6256598B2 (enrdf_load_stackoverflow) | ||
| KR840005634A (ko) | 클럭 재생회로 | |
| JP2624142B2 (ja) | スキャンテスト用クロック発生回路 | |
| JP2710853B2 (ja) | パルスジェネレータ | |
| JP2667702B2 (ja) | ポインタリセット方式 | |
| JP2548500Y2 (ja) | Ic試験装置の波形整形装置 | |
| JP2854407B2 (ja) | パルスジェネレータ | |
| JPS5934939Y2 (ja) | メモリのアドレス指定回路 | |
| JP2548501Y2 (ja) | Ic試験装置の波形整形装置 | |
| JPH04207216A (ja) | 非重複2相クロック発生回路 | |
| JPS59167117A (ja) | 直列−並列変換回路 | |
| JP2528965B2 (ja) | クロック位相制御回路 | |
| JP2660688B2 (ja) | 論理波形発生装置 | |
| JPS6226743B2 (enrdf_load_stackoverflow) | ||
| JPH0350453B2 (enrdf_load_stackoverflow) | ||
| JPH045292B2 (enrdf_load_stackoverflow) | ||
| JPH0637627A (ja) | カウンタ読込み方式 |