JPS62137635A - Bit pattern detecting device - Google Patents

Abstract

PURPOSE:To make it possible to recognize which bit pattern is selected from the content of an outputted pattern detection signal by writing bit pattern detection signal data of desired content in the address of a memory circuit beforehand. CONSTITUTION:A user inputs plural bit patterns [110X], [101X], [11X1] and corresponding desired bit pattern detection signal data [01], [10], [11] from a pattern inputting section 10. A control section 12 writes data [01] in addresses [1101], [1100] of a memory circuit 18, and writes data [10] in addresses [1011], [1010], and writes data [11] in addresses [1111], [1101], and writes ineffective data [00] in other addresses. Under this condition, in the controlling section 12, [01] is outputted as a pattern detection signal (d) when external data is [110X], [10] is outputted when [101X] and [11] is outputted when [11X1]. Thus, bit patterns can be detected immediately.

Description

[Detailed Description of the Invention] Description of the Technical Field The present invention relates to a device for detecting a predetermined bit pattern from bit data generated by an external force, and a device that can arbitrarily set the contents of a bit pattern detection signal. : Regarding fc position.

Description of the Prior Art Conventionally, the system is manually operated continuously from outside. Any bit pattern of bit data such as control data or address data of the CPU? A device as shown in FIG. 2 is known as a detection device.

That is, the bit pattern to be detected is manually set to one side of the comparator 2 by the register 1 (or switch, etc.). Also, the external data is masked by the gate circuit 3 and the register 5 that stores the mask pattern (a specific digit of the external data is fixed to "O" or "1" by the mask pattern), and the other input terminal of the comparator 2 is is input. When the input external data matches the bit pattern in the register 1, the comparator 2 outputs a bit pattern detection signal. Further, since only one bit pattern can be set in the register 1, similarly configured circuits are connected in parallel in order to detect a plurality of bit patterns.

For this reason, the conventional device has the drawbacks of an increased number of parts, poor manufacturing efficiency, and high cost. Furthermore, the content of the bit pattern detection signal is also one type (for example, ON or 0F).
F) When detecting a plurality of bit patterns without being able to obtain L, there are drawbacks such as the inability to associate each bit pattern with the contents of its bit pattern ejection signal.

Purpose of the Present Invention The present invention improves this point, and can reduce the number of parts and the board area.
It is an object of the present invention to provide a bit pattern detection device that can be set as follows.

Outline of the Present Invention The present invention includes a memory circuit capable of writing and reading data, and a saliva suppressing circuit, wherein the collateral circuit detects the memory circuit no trace corresponding to a bit pattern to be detected in an initialization mode. The desired bit pattern detection data is written to this address, and invalid data (for example, rooJ) is written to other addresses.
) In the e-write operation mode, the address of the storage circuit is accessed using external bit data, and when the external bit data is a gushing pattern, the bit pattern detection data is controlled to be read. .

Explanation by example An embodiment of the present invention will be described based on the drawings.

Figure @1 shows a block diagram of main parts of an embodiment of the present invention.

In Figure 11, 210 indicates a pattern input section for the user to input a bit pattern to be detected. This pattern input section 10 is connected to a control section 12 via an interface section 11.

A storage circuit 16 storing control programs, mask programs, etc. is connected to the control section 12. Further, selectors 16 and 17 . Connect the memory circuit 18.

To explain the characteristic operation of the embodiment of the present invention configured in this way, the user puts the control unit 12 into the initialization mode, and the bit pattern (hereinafter referred to as "bit pattern") that the user wants to detect.

It is simply called the "bit pattern". ) and bit pattern detection signal data of desired content (for example, rolJ) are input from the input unit 10. At this time, the hit pattern can be masked and input. For example, if the bit pattern is entered manually, the lowest focus will be masked.

The control unit 12 uses this input bit pattern r101.
All applicable patterns from Xj "1011J,
Find l'-1010J. In initialization mode selectors 16 and 17 are A1 and A2 respectively.
'AQ is selected, and the control unit 12 selects the bit pattern r1tlIXj (i.e., A, side).

1011 and 1010) are output to the address bus 19 of the memory circuit 18, and the bit pattern detection signal data "01" is output to the data bus 20 of the A2 measurement circuit 18.
Output. As a result, the bit pattern detection signal data is written to each address of the storage circuit 18 specified by the bit pattern to be detected. At this time, invalid data, such as rU O
J, is written.

In this state, the user controls the control section 12 to control the pattern input section 10.
When the operation mode is set, selectors 16 and 17 are selected to the B, hexagram, and B2 sides, and external data D is input to the address bus 19 of the memory circuit 18. The storage circuit 18 is accessed with this external data D, and when the external data D matches the bit pattern, the bit pattern detection signal data "01" is outputted to the output terminal 21 as the bit pattern detection signal d. This pattern detection signal d
It is a feature of the present invention that the content of the information can be set in advance to a desired content. This feature of the present invention is most effectively utilized when a plurality of bit patterns are set.

That is, if the user selects multiple bit patterns, rl 1
0XJ, rl01XJ, rlIXIJ and corresponding desired bit pattern detection signal data r01j, r1tj4, "11" are input from the pattern person υ unit 10. The control unit 12 operates in the same manner as described above to set the address "1101J" of the memory circuit 18.

Write data "01" to 1-1100J, write data "10" to address [101J, write data "10" to address "1011J, write data "11" to l-1101J, invalidate other addresses. data"
00” is written.

In this state, when the control unit 12 is set to the operation mode, the pattern detection signal d is output as "01" when the external data is rl 10XJ, and 1'-101X
When J, the pattern detection signal d is "10",
When rlIXIJ, "11" is output as the pattern detection signal d. Therefore, when a plurality of bit patterns are set, each bit pattern can be associated with a pattern detection signal, and it is possible to immediately recognize which bit pattern has been ejected based on the content of the pattern detection signal. This is a feature of the present invention.

Further, although the above embodiment shows an example of 4 bits, the present invention is not limited to this. Further, although the explanation has been made using invalid data eroOj, the present invention is not limited to this.

Description of Effects As explained above, according to the present invention, the address of the memory circuit is specified by the bit pattern data to be detected, the bit pattern detection signal data of the desired content is written in advance to this address, and the memory circuit is detected by the external data. The device is configured to output the bit pattern detection signal data as a bit pattern detection signal when the bit pattern is accessed and the external data match. Therefore, compared to conventional devices, the number of parts can be significantly reduced, and the board area can also be significantly reduced. Moreover, when multiple bit patterns are set to be detected, each bit pattern and its corresponding The bit pattern detection signal can be associated with the bit pattern detection signal, and the operation processing in the next-level device based on the bit pattern detection can be facilitated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. FIG. 2 is an explanatory diagram of a conventional device. 12...Se1j saliva part 16.17...Selector 18...Memory circuit. Patent applicant: System One Co., Ltd. (5 other people)

Claims (2)

[Claims] (1) A bit pattern detection device that detects a predetermined bit pattern from bit data input from the outside, which includes a storage circuit and detection of a bit pattern of desired content at an address of the storage circuit corresponding to the bit pattern to be detected. a first control circuit that writes signal data; and a first control circuit that accesses the storage circuit with the bit data input from the outside and generates the bit pattern detection signal when the bit pattern to be detected matches the bit data input from the outside. A bit pattern detection device comprising: a second control circuit that outputs data as a bit pattern detection signal. (2) The bit pattern to be detected is of at least two types, and the bit pattern detection signal data corresponds to the bit pattern to be detected and has different contents. The bit pattern detection device according to scope (1).