JPS62128116A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62128116A
JPS62128116A JP26845985A JP26845985A JPS62128116A JP S62128116 A JPS62128116 A JP S62128116A JP 26845985 A JP26845985 A JP 26845985A JP 26845985 A JP26845985 A JP 26845985A JP S62128116 A JPS62128116 A JP S62128116A
Authority
JP
Japan
Prior art keywords
oxide film
ions
ion
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26845985A
Other languages
Japanese (ja)
Inventor
Hiroshi Onoda
小野田 宏
Shinichi Sato
真一 佐藤
Mikio Nishihata
西畑 幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26845985A priority Critical patent/JPS62128116A/en
Publication of JPS62128116A publication Critical patent/JPS62128116A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize formation of a contact part in a small area, by irradiating a part of an oxide film with ions having much reducibility and having it get conductivity by reduction so that reliability of electrical contact is improved between an upper wiring and a lower silicon substrate. CONSTITUTION:After a silicon oxidizing film 2 is formed with thickness of 1mum or so on a silicon substrate 1, H<+>2 ion beams 5 or the like are implanted with a dose amount of 10<18>ps/cm<3> or less and acceleration voltage of 20kV or so within about 1X1mum<2> area of a place in which a contact part 3 is to be formed. Thereafter, an upper wiring 4 is formed on the oxidizing film 2. Ion implantation may be performed at the contact part by an implantation process such as a general phototype process and a nonfocussed ion beam implantation process. Any material is available for an oxidizing film used as a layer insulating film, if the material oxidized by it has conductivity. Besides, any ion is available for a kind of an implanting ion as long as it has reducibility. Particularly, CO<+> ion beams are preferable because it can be changed into volatile CO2 by a reducing reaction.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の製造方法に関し、さらに詳し
くは層間絶縁膜を介した上層部の配線と下層部のシリコ
ン基板との電気的接触に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to electrical contact between wiring in an upper layer and a silicon substrate in a lower layer via an interlayer insulating film. It is something.

〔従来の技術〕[Conventional technology]

第2図+a)〜fclは従来の半導体装置の製造方法に
おける順次の工程を示す断面図であり、図において、(
1)はシリコン基板、(2)はシリコン基板(1)上に
形成された層間絶縁膜としてのシリコン酸化膜、(3)
は酸化膜(2)に穿設されたコンタクト孔、(4)はコ
ンタクト孔(3)を含む酸化膜(2)の上面に蒸着また
はスバ、り堆積された上層部配線(配線(4)には電極
部分も含まれる。以下同様)である。
FIG. 2 +a) to fcl are cross-sectional views showing sequential steps in a conventional semiconductor device manufacturing method;
1) is a silicon substrate, (2) is a silicon oxide film as an interlayer insulating film formed on the silicon substrate (1), (3)
(4) is the contact hole drilled in the oxide film (2), and (4) is the upper layer wiring (wiring (4)) deposited by vapor deposition or thin film on the upper surface of the oxide film (2) including the contact hole (3). (includes the electrode part; the same applies hereafter).

次に、工程について説明する。ソースおよびドレインの
形成工程を終えたシリコン基板(1)上に第2図fat
に示すように酸化膜(2)を1μmの厚さに堆積する。
Next, the process will be explained. Figure 2 shows a fat layer on the silicon substrate (1) after the process of forming the source and drain.
An oxide film (2) is deposited to a thickness of 1 μm as shown in FIG.

続いて、フォトレジストを酸化膜(2)に塗布し紫外線
で露光して現像した後に2×2μm2程度のコンタクト
孔のパターンを形成する。その後、酸化膜(2)をCH
F xガスでドライエツチングし、第2図(blに示す
ようにコンタクト孔(3)を形成する。そして、コンタ
クト孔(3)を含む酸化膜(2)の全面にAβまたはA
j!Si合金をスパッタ蒸着し、さらに写真製版工程な
らびにエツチング工程により、第2図fclに示すよう
に上層部配線(4)を形成す〔発明が解決しようとする
問題点〕 従来の半導体装置の製造方法は以上のように構成されて
いるので、コンタクト孔(3)の大きさが2×2μm2
程度までは第3図ta+に示すようにスパッタ渾着され
たA6またはAj!Si合金はコンタクト孔(3)の底
部までなだらかに堆積し、上層部配線(4)と下層部の
シリコン基板(1)とは十分な電気的接触をとることが
できる。しかし、現在量も微細な素子として試作されつ
つぁるIMD−RAMや数年後に現れると予想される4
MD−RAM等ではコンタクト孔(3)の大きさはさら
に微細化され、特に後者では1−×1μm2程度の大き
さになるであろうと予想される。コンタクト孔(3)の
大きさが1×1μm2程度の場合、従来の製造方法では
第3図(b)に示すようにコンタクト孔(3)内に十分
に上層部配線(4)が形成されず、上層部配* f41
とシリコン基板(1)の電気的接触が悪化し、この結果
、高抵抗または断線が生じるというおそれがある。これ
を解決するために、テーパエツチング法やさまざまなコ
ンタクト孔の平坦化技術が提案されているが未だ決定的
な解決手段はないという問題点があった。
Subsequently, a photoresist is applied to the oxide film (2), exposed to ultraviolet light, and developed, after which a pattern of contact holes of about 2×2 μm 2 is formed. After that, the oxide film (2) is
Dry etching is performed with Fx gas to form a contact hole (3) as shown in FIG.
j! A Si alloy is sputter-deposited, and an upper layer wiring (4) is formed as shown in FIG. 2 fcl by a photolithography process and an etching process. is constructed as described above, so the size of the contact hole (3) is 2 x 2 μm2.
As shown in Fig. 3 ta+, sputter-bound A6 or Aj! The Si alloy is deposited gently to the bottom of the contact hole (3), and sufficient electrical contact can be made between the upper wiring (4) and the lower silicon substrate (1). However, IMD-RAM, which is currently being prototyped as a microscopic device, and 4 which are expected to appear in a few years.
In MD-RAMs and the like, the size of the contact hole (3) will be further miniaturized, and in the latter case in particular, it is expected that the size will be about 1-x1 μm2. When the size of the contact hole (3) is about 1 x 1 μm2, the upper layer wiring (4) cannot be sufficiently formed in the contact hole (3) using the conventional manufacturing method, as shown in Figure 3(b). , upper management* f41
The electrical contact between the silicon substrate (1) and the silicon substrate (1) may deteriorate, resulting in high resistance or disconnection. To solve this problem, taper etching methods and various contact hole flattening techniques have been proposed, but there is still no definitive solution.

この発明は上記のような問題点を解消するためになされ
たもので、コンタクト孔が微小化されても上層部配線と
下層部のシリコン基板との電気的接触を良好に保つこと
のできる半導体装置の製造方法を得ることを目的とする
This invention was made to solve the above-mentioned problems, and provides a semiconductor device that can maintain good electrical contact between the upper wiring and the lower silicon substrate even if the contact hole is miniaturized. The purpose is to obtain a manufacturing method for.

また、この発明の別の発明は、さらに酸化膜中の酸素と
イオンとの化合により生じる化合物を除去してコンタク
ト部の導電性を良好に保つことのできる半導体装置の製
造方法を得ることを目的とする。
Another object of the present invention is to provide a method for manufacturing a semiconductor device that can maintain good conductivity in a contact area by removing compounds generated by the combination of oxygen and ions in an oxide film. shall be.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置の製造方法は、眉間絶縁膜で
ある酸化膜上のコンタクト孔のあるべき箇所に還元性の
強いイオンを注入し、コンタクト孔となるべき部分の酸
化膜を還元して導電性を持たせることにより、上層部配
線と下層部のシリコン基板との電気的接触をとるように
したものであまた、この発明の別の発明に係わる半導体
装置の製造方法は、さらに酸化膜中の酸素とイオンとの
結合により生じる化合物を除去するようにしたものであ
る。
The method for manufacturing a semiconductor device according to the present invention involves implanting strongly reducing ions into the part of the oxide film that is the glabella insulating film where the contact hole should be, reducing the oxide film in the part that should become the contact hole and making it conductive. The method for manufacturing a semiconductor device according to another aspect of the present invention further provides an electrical contact between the upper layer wiring and the lower layer silicon substrate by imparting properties to the oxide film. It is designed to remove compounds produced by the combination of oxygen and ions.

〔作用〕[Effect]

この発明における還元性の強いイオンを照射する工程は
、コンタクト部の酸化膜を還元して導電性を持たせ、上
層部配線と下層部のシリコン基板とを電気的に接触させ
る。すなわち、本発明は酸化物に還元性の強いイオンを
注入すると酸化物の一部が次の反応式により還元される
ことを利用したものである。なお、M、O,は酸化物、
Iは注入イオン、m、nおよびpは価数である。
In the step of irradiating highly reducing ions in the present invention, the oxide film in the contact portion is reduced to have conductivity, and the upper layer wiring and the lower layer silicon substrate are brought into electrical contact. That is, the present invention utilizes the fact that when strongly reducing ions are implanted into an oxide, a portion of the oxide is reduced according to the following reaction formula. In addition, M, O, are oxides,
I is the implanted ion, m, n and p are the valence numbers.

MIIOII+pInM+1.Oll したがって、物質Mが導電性を持つものであれば、イオ
ンを注入し還元を行うことにより酸化物の一部に導電性
を持たせることができる。
MIIOII+pInM+1. Therefore, if the substance M has conductivity, a part of the oxide can be made conductive by implanting ions and performing reduction.

また、この発明の別の発明における化合物の除去工程は
、コンタクト部に不純物が残留するのを防止し、コンタ
クト部の導電性を良好に保つ。
Further, the compound removal step in another aspect of the present invention prevents impurities from remaining in the contact portion and maintains good conductivity of the contact portion.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。M1
図において、(1)はシリコン基板、(2)はシリコン
酸化膜、(3)はコンタクト部、(4)は上層部配線、
(5)は照射する還元性の強い水素イオンビームである
An embodiment of the present invention will be described below with reference to the drawings. M1
In the figure, (1) is a silicon substrate, (2) is a silicon oxide film, (3) is a contact part, (4) is an upper layer wiring,
(5) is a highly reducing hydrogen ion beam.

次に、工程について説明する。第1図(alに示すよう
にシリコン基板(1)上にシリコン酸化膜(2)を1μ
mの厚さで形成した後、第1図(blに示すようにコン
タクト部(3)を形成すべき箇所の1×1μm2の領域
にH2+イオンビーム(5)を加速電圧20KVでlO
I′1個/Cm”以下のドーズ量で注入する。
Next, the process will be explained. As shown in Figure 1 (al), a silicon oxide film (2) of 1μ
After forming the contact portion (3) to a thickness of 1.0 m, as shown in FIG.
The implantation is performed at a dose of I'1/Cm" or less.

この後、第り図tc+に示すように上層部配線(4)を
酸化膜(2)上に形成する。
Thereafter, as shown in Figure tc+, an upper layer wiring (4) is formed on the oxide film (2).

完成後に半導体装置の信頼性を測定したところ、従来の
方法で1×1μm2のコンタクト孔を形成した場合より
もはるかに信頼性が向上したことが確認できた。
When the reliability of the semiconductor device was measured after completion, it was confirmed that the reliability was much improved compared to when contact holes of 1×1 μm 2 were formed using the conventional method.

なお、本実施例ではイオン注入工程に電界電離型ガスイ
オン源を用いたが、一般的な写真製版工程と非集束イオ
ンビームによる注入工程によりコンタクト部にイオン注
入してもよい。
In this embodiment, a field ionization type gas ion source was used for the ion implantation process, but ions may be implanted into the contact portion by a general photolithography process and an implantation process using a non-focused ion beam.

また、層間絶縁膜として用いられる酸化膜もその被酸化
物質が導電性を持つものであれば何でもよい。酸化膜中
の酸素とイオンが反応して生じる化合物がコンタクト部
の良好な導電性を阻害するものである場合には、イオン
照射の工程の後にこの化合物の除去工程を行うことが望
ましい。
Moreover, any oxide film used as the interlayer insulating film may be used as long as the substance to be oxidized has conductivity. If a compound produced by the reaction of oxygen and ions in the oxide film inhibits good conductivity of the contact portion, it is desirable to perform a step of removing this compound after the ion irradiation step.

また、注入するイオン種は還元力があれば何でもよいが
、特に、Co1イオンビームなどは還元反応を経た後に
揮発性のCO□となるため、コンタクト部に不純物が残
らずイオンビームとしてより適している。
In addition, any ion species to be implanted may be used as long as it has reducing power, but Co1 ion beams in particular become volatile CO□ after undergoing a reduction reaction, so they do not leave impurities in the contact area and are more suitable as ion beams. There is.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば酸化膜の一部を還元す
ることにより導電性を持たせこの部分をコンタクト部と
するので、従来の半導体装置の製造方法に比べて上層部
配線はほとんど平坦なコンタクト部を介してシリコン基
板と電気的接触を行うことができ、上層部配線と下層部
のシリコン基板との電気的接触の信頼性が高いものが得
られる効果がある。また、従来の方法よりはるかに小さ
な面積のコンタクト部の形成が可能であり、工程も従来
の製造方法よりはるかに簡略化されたものが得られる効
果がある。
As described above, according to the present invention, a part of the oxide film is reduced to make it conductive and this part is used as a contact part, so the upper layer wiring is almost flat compared to the conventional semiconductor device manufacturing method. Electrical contact can be made with the silicon substrate through the contact portion, which has the effect of providing highly reliable electrical contact between the upper wiring and the lower silicon substrate. Furthermore, it is possible to form a contact portion with a much smaller area than in the conventional method, and the manufacturing process is also much simpler than in the conventional method.

また、この発明の別の発明によれば、さらにイオンの照
射の結果酸化膜中に生じた化合物を除去するので、コン
タクト部の導電性を良好に保つことができる。
Further, according to another aspect of the present invention, compounds generated in the oxide film as a result of ion irradiation are further removed, so that good conductivity of the contact portion can be maintained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(clはこの発明の一実施例による半導
体装置の製造方法における順次の工程を示す断面図、第
2図(al〜(C)は半導体装置の製造方法における順
次の工程を示す断面図、第3図(a)は従来の半導体装
置の製造方法によるコンタクト孔の大きさが2×2μm
2程度のときの断面図、第3図(blは従来の半導体装
置の製造方法によるコンタクト孔の大きさが1×1μm
2のときの断面図である。 (1)はシリコン基板、(2)は酸化膜、(3)はコン
タクト部、(4)は上層部配線、(5)は水素イオンビ
ーム。 なお、図中、同一符号は同一または相当部分を示す。
FIG. 1 (al~(cl) is a cross-sectional view showing the sequential steps in the method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. The cross-sectional view shown in FIG. 3(a) shows that the size of the contact hole is 2×2 μm according to the conventional semiconductor device manufacturing method.
Fig. 3 is a cross-sectional view when the size of the contact hole is approximately 1 x 1 μm (bl is 1 x 1 μm).
FIG. (1) is a silicon substrate, (2) is an oxide film, (3) is a contact portion, (4) is an upper layer wiring, and (5) is a hydrogen ion beam. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (6)

【特許請求の範囲】[Claims] (1)シリコン基板上に酸化膜を形成する工程と、上記
酸化膜上のコンタクト孔を形成すべき箇所に還元力の強
いイオンを照射し上記酸化膜の一部を還元してコンタク
ト部を形成する工程と、このコンタクト部を含む上記酸
化膜上に上層部配線を形成する工程とを含むことを特徴
とする半導体装置の製造方法。
(1) A step of forming an oxide film on a silicon substrate, and irradiating a portion of the oxide film where a contact hole is to be formed with ions with strong reducing power to reduce a part of the oxide film to form a contact portion. A method for manufacturing a semiconductor device, comprising the steps of: forming an upper layer wiring on the oxide film including the contact portion.
(2)シリコン基板上に酸化膜を形成する工程と、上記
酸化膜上のコンタクト孔を形成すべき箇所に還元力の強
いイオンを照射し上記酸化膜の一部を還元してコンタク
ト部を形成する工程と、上記酸化膜中で酸素と上記イオ
ンとが結合した化合物を除去する工程と、上記コンタク
ト部を含む上記酸化膜上に上層部配線を形成する工程と
を含むことを特徴とする半導体装置の製造方法。
(2) A step of forming an oxide film on the silicon substrate, and irradiating a portion of the oxide film where a contact hole is to be formed with ions with strong reducing power to reduce a part of the oxide film to form a contact part. a step of removing a compound in which oxygen and the ion are bonded in the oxide film; and a step of forming an upper wiring on the oxide film including the contact portion. Method of manufacturing the device.
(3)上記還元力の強いイオンとして水素イオンを用い
ることを特徴とする特許請求の範囲第1項または第2項
記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that hydrogen ions are used as the ions with strong reducing power.
(4)上記還元力の強いイオンとして一酸化炭素イオン
を用いることを特徴とする特許請求の範囲第1項または
第2項記載の半導体装置の製造方法。
(4) The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that carbon monoxide ions are used as the ions with strong reducing power.
(5)上記イオンを照射する酸化膜として二酸化シリコ
ンを用いることを特徴とする特許請求の範囲第1項また
は第2項記載の半導体装置の製造方法。
(5) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein silicon dioxide is used as the oxide film to which the ions are irradiated.
(6)上記イオンを照射するイオン源として電界電離型
ガスイオン源を用いることを特徴とする特許請求の範囲
第1項または第2項記載の半導体装置の製造方法。
(6) A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that a field ionization type gas ion source is used as the ion source for irradiating the ions.
JP26845985A 1985-11-28 1985-11-28 Manufacture of semiconductor device Pending JPS62128116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26845985A JPS62128116A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26845985A JPS62128116A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62128116A true JPS62128116A (en) 1987-06-10

Family

ID=17458797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26845985A Pending JPS62128116A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62128116A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4325706A1 (en) * 1992-07-31 1994-02-10 Toshiba Kawasaki Kk Mfg. electrode or wiring layer on semiconductor device - forming metal oxide film and reducing to produce wiring layer e.g. of copper or silver
JP2015528198A (en) * 2012-06-21 2015-09-24 モナッシュ ユニバーシティMonash University Conductive part of insulating material

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4325706A1 (en) * 1992-07-31 1994-02-10 Toshiba Kawasaki Kk Mfg. electrode or wiring layer on semiconductor device - forming metal oxide film and reducing to produce wiring layer e.g. of copper or silver
US5424246A (en) * 1992-07-31 1995-06-13 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor metal wiring layer by reduction of metal oxide
DE4325706C2 (en) * 1992-07-31 2002-08-29 Toshiba Kawasaki Kk Method for producing a semiconductor device
JP2015528198A (en) * 2012-06-21 2015-09-24 モナッシュ ユニバーシティMonash University Conductive part of insulating material

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