JPS62125680A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62125680A
JPS62125680A JP26640485A JP26640485A JPS62125680A JP S62125680 A JPS62125680 A JP S62125680A JP 26640485 A JP26640485 A JP 26640485A JP 26640485 A JP26640485 A JP 26640485A JP S62125680 A JPS62125680 A JP S62125680A
Authority
JP
Japan
Prior art keywords
film
photoresist
recess
hole
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26640485A
Other languages
Japanese (ja)
Inventor
Susumu Kubota
窪田 勧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26640485A priority Critical patent/JPS62125680A/en
Publication of JPS62125680A publication Critical patent/JPS62125680A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a gate length shorter than a hole width of a photoresist by inclining and dry etching a semiconductor substrate covered with an insulating film, narrowing the width of a recess hole as seen from a normal line, and then adding a gate metal. CONSTITUTION:An oxide film 2 is grown on a semiconductor substrate 1, a nitride film 3 is further grown thereon, a photoresist 5 coated, exposed and developed on the wafer formed with the insulating film to form a photoresist 5 having a hole. Then, the wafer is inclined in an anisotropically dry etching direction, anisotropically dry etched to etch the film 3 to form a hole different from the hole of the photoresist in the film 3. The film 2 is removed by set etching until arriving at the substrate 1, a recess is formed on the substrate 1 by etching, anodic oxidation method, and with the film 3 as a mask a gate metal 4 is added in the recess by a depositing method. Thus, an MESFET having a short gate length is simply manufactured.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に絶縁膜を
マスクとして、リセス型のM r−、 S F E T
のゲート金属を付設する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular, using an insulating film as a mask, recessed M r-, S F E T
The present invention relates to a method of attaching gate metal.

1′従来の技術〕 従来、リセス型のM E 8 FETのグー1〜金属の
付設にあたっては、まずフt l−レジスI・をマスク
とし絶縁膜に開11部を設番するが開L1にあたっては
半導体基板を平板トに水平に置き、平板の法線方向から
W方性l・ライエツチングを行っていたため、形成され
る絶縁膜の開口部は第3図に示ずようにフォトレジスト 形成後、蒸着によって付設されるケーI・金属のゲ− 
1−長はフォトレジストーの開口部よりも短くすること
は出来なかった。
1' Conventional technology] Conventionally, when attaching metal to the recessed ME8 FET, first, an opening 11 was created in the insulating film using the resist I as a mask, but when opening L1 Because the semiconductor substrate was placed horizontally on a flat plate and the W-oriented l-ly etching was performed from the normal direction of the flat plate, the opening of the insulating film formed was formed after the photoresist was formed, as shown in Figure 3. , metal gate attached by vapor deposition
1-length could not be made shorter than the photoresist opening.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

L述したように、従来のゲート金属付設法では、ゲート
長がフォトレジスト 依存しているため、よりグー1へ長を短かくして特性の
よいM E SF E Tを得ることができなく、より
微細なフォlーレジスl−のりソグラフィが要求されて
いた6又微細化にともなう歩留り低下、コス1−5労力
の増大という問題かあ−)た。
As mentioned above, in the conventional gate metal attachment method, the gate length depends on the photoresist, so it is not possible to shorten the gate length to obtain a M E SF E T with good characteristics. There were problems such as a decrease in yield and an increase in cost and labor due to the miniaturization of the hexagonal resistor, which required lithography.

本発明の]−1的は、ウェーハの法線方向から見た絶縁
膜の開11部をフオI〜レジスI〜の開1]1部より幅
を短くでき、ゲート長の短いM +”、 S F ET
を簡jiiに製造できる゛l’導体装置の製造方法を提
供することにある。
[-1] of the present invention is that the width of the opening 11 of the insulating film viewed from the normal direction of the wafer can be made shorter than that of the opening 1 of the resist I, and the gate length can be shortened. SFET
An object of the present invention is to provide a method for manufacturing a conductor device that can be easily manufactured.

〔問題点を解決するための手段1 本発明の半導体装置の製造方法は、リセス型のMESF
ETを製造する工程で、半導体基板上を被覆した絶縁膜
を、フォトレシスI−をマスクとし異方性ドライエツチ
ングで除去して、リセス部の開口を行う際に、半導体基
板を傾斜させて異方性トライエ・ソチンクすることによ
り半導体基板の法線方向から見たリセス開11部の幅を
狭くて、蒸着法でグー1〜金属をイ・1設し、)第1・
レジスI・の開口幅よりも短いゲート長がt′、Yられ
るという特徴を有している。
[Means for Solving the Problems 1] The method for manufacturing a semiconductor device of the present invention includes a recessed MESF
In the process of manufacturing an ET, the insulating film covering the semiconductor substrate is removed by anisotropic dry etching using Photoresis I- as a mask, and when opening a recess, the semiconductor substrate is tilted and anisotropic dry etching is performed. The width of the recess opening 11 as seen from the normal direction of the semiconductor substrate is narrowed by performing a chemical trial and socing process, and the metals 1 to 1 are deposited using a vapor deposition method.
It has the characteristic that the gate length t' and Y is shorter than the opening width of the resistor I.

[実施例] 次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例により形成されたM P、
 8F E Tの縦断面図であり、又第2図は本発明の
一実施例を説明するための一部工程の縦断面図である1
、 まず、第1図、第2図に示すように、半導体基板1の表
向上に酸化膜2を成長させ、さらにその−にに窒化膜3
を成長させる。
[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 shows an MP formed according to an embodiment of the present invention;
FIG. 2 is a vertical cross-sectional view of a partial process for explaining an embodiment of the present invention.
First, as shown in FIGS. 1 and 2, an oxide film 2 is grown on the upper surface of a semiconductor substrate 1, and then a nitride film 3 is grown on the top surface of the semiconductor substrate 1.
grow.

次いで、−J−配給縁膜の形成されたウェーハにフォ1
ヘレジス1〜5を塗布・露光 現像し開口部を有するフ
才)ヘレジスl−5を形成する。
Next, the wafer on which the -J-distribution film was formed was exposed to a photo 1 film.
Heregis 1 to 5 are coated, exposed, and developed to form a sheet with openings) Heregis 1-5.

次に、第2図に示すように、ウェーハを異方性ドライエ
ツチング方向に対し傾斜して設置し、異方性ドライエツ
チングを行って窒化膜をエツチングすると図示のように
フォ1〜レジスト開口部と異なった開口が窒化膜に形成
される。
Next, as shown in FIG. 2, the wafer is placed at an angle with respect to the anisotropic dry etching direction, and the nitride film is etched by anisotropic dry etching. Different openings are formed in the nitride film.

次いで、ウェッI〜エツチングで酸化膜2を半導体基板
1に達するまで除去し、次いでエツチング。
Next, the oxide film 2 is removed by wet etching until it reaches the semiconductor substrate 1, and then etched.

陽極酸化法等で半導体基板1にリセスを形成する。A recess is formed in the semiconductor substrate 1 by an anodic oxidation method or the like.

次いて、第1図に示すように窒化膜3をマスクとして、
従来と同様の蒸着法により、グー1−メタル4をリセス
内に付設する。
Next, as shown in FIG. 1, using the nitride film 3 as a mask,
Goo 1-metal 4 is attached in the recess by a conventional vapor deposition method.

以上により、フォトレジスト〜の開口部の幅よりも短い
グー1〜長が、簡単に得られ、酸化膜、窒化膜の厚さ、
傾斜する角度などの染件を最適化すれば、リセス内での
ケートのオフセ・l、 I−も可能である。
With the above, it is easy to obtain a length of Gou1 which is shorter than the width of the opening of the photoresist, and the thickness of the oxide film and nitride film,
By optimizing conditions such as the angle of inclination, it is also possible to offset the gates within the recess.

〔発明の効県〕[Effect of invention]

以」ユ説明したように本発明は、リセス型のMESFE
Tのケーl〜を形成する]二程で、絶縁膜の開口を行う
際、ウェーハを傾斜させてフォトレジストをマスクに用
い、絶縁膜を異方性ドライエツチングすることにより、
ウェーハの法線方向から見た絶′縁膜の開[1部をフオ
トレジス1〜の開口部よりも幅を短くでき、この開口部
をマスクとしてゲート金属を蒸着すると、グー1〜長の
短いMESFETを簡単に製造でき、微細化され性能の
優れた半導体装置を高歩留り、低コス1〜に得ることが
できる。
As explained above, the present invention is a recess type MESFE.
In step 2, when opening the insulating film, the wafer is tilted, the photoresist is used as a mask, and the insulating film is anisotropically dry etched.
The width of the opening [1] of the insulating film viewed from the normal direction of the wafer can be made shorter than the opening of the photoresist 1~, and when gate metal is evaporated using this opening as a mask, MESFET with a short length of goo 1~ can be made. It is possible to easily manufacture a miniaturized semiconductor device with excellent performance at a high yield and at a low cost of 1~.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例により形成された=9− 半導体装置の縦断面図、第2図は、本発明の一実施例を
説明するための一部工程の縦断面図、第3図は、従来の
半導体装置のデー1−金属を蒸着した後の断面図である
。 1・・半導体基板、2・・・酸化膜、3・・・窒化膜、
4・・ゲート金属、5・・・フォl−レジスl〜。 代理人 弁理士  内 原  晋 −ら−
FIG. 1 is a longitudinal cross-sectional view of a =9- semiconductor device formed according to an embodiment of the present invention, and FIG. 2 is a longitudinal cross-sectional view of a partial process for explaining an embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional semiconductor device after metal has been deposited. 1... Semiconductor substrate, 2... Oxide film, 3... Nitride film,
4... Gate metal, 5... Fol-Resist l~. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 半導体基板を被覆した絶縁膜をフォトレジストをマスク
とし異方性ドライエッチングで絶縁膜を除去してリセス
部の開口を行う工程を有する半導体装置の製造方法にお
いて、前記絶縁膜で被覆されフォトレジストへのマスク
の形成された半導体基板を傾斜させて異方性ドライエッ
チングすることにより半導体基板の法線方向から見たリ
セス開口部の幅を狭くした後、蒸着法でゲート金属を付
設し、フォトレジストの開口幅よりも短いゲート長を得
ることを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device, the method includes a step of removing an insulating film covering a semiconductor substrate using a photoresist as a mask and opening a recess by removing the insulating film by anisotropic dry etching using a photoresist as a mask. After narrowing the width of the recess opening seen from the normal direction of the semiconductor substrate by tilting the semiconductor substrate on which the mask is formed and performing anisotropic dry etching, gate metal is attached by vapor deposition, and photoresist is etched. A method for manufacturing a semiconductor device characterized by obtaining a gate length shorter than an aperture width.
JP26640485A 1985-11-26 1985-11-26 Manufacture of semiconductor device Pending JPS62125680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26640485A JPS62125680A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26640485A JPS62125680A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62125680A true JPS62125680A (en) 1987-06-06

Family

ID=17430459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26640485A Pending JPS62125680A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62125680A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849638A (en) * 1996-03-04 1998-12-15 International Business Machines Corporation Deep trench with enhanced sidewall surface area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849638A (en) * 1996-03-04 1998-12-15 International Business Machines Corporation Deep trench with enhanced sidewall surface area
US6153474A (en) * 1996-03-04 2000-11-28 International Business Machines Corporation Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate

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