JPS62120721A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To apply stable voltage controlled oscillation over a wide range even when a power voltage of a PLL is a low voltage by providing a boosting means between a phase comparison means and a voltage controlled oscillation means so as to apply a large DC voltage to the voltage controlled oscillation means. CONSTITUTION:An output voltage e1 of a tank circuit 231 is boosted to a large voltage e2 by a boosting means being a transformer 233, rectified by a rectifier circuit 235, its rectified signal 237 is smoothed through a low-pass filter 239 to obtain a DC voltage signal 221. A voltage controlled oscillator VCO 223 consists of, e.g., a varactor diode and its capacitance is controlled variably in response to a DC voltage of the DC voltage signal 221. Thus, an oscillated output frequency fout of the output signal 225 of the VCO 223 is controlled. Then even when a low voltage supply is used for the PLL power supply, the DC control voltage 221 sufficiently for the voltage controlled oscillation of the VCO 223 properly over a wide range is obtained.

Description

[Detailed Description of the Invention] [Summary] This is a phase-locked loop circuit, in which a step-up means is provided between the phase comparison means and the voltage-controlled oscillation means, so that a large DC voltage can be applied to the voltage-controlled oscillation means. configure,
Even if the circuit power supply is configured with a low voltage system, phase lock can be applied over a wide range.

[Industrial application field]

The present invention relates to a phase-locked loop circuit, and more particularly to a phase-locked loop circuit that can supply a voltage sufficient to drive a voltage-controlled vibrator even when the operating voltage of the circuit system is lowered.

[Conventional technology]

Such a phase-locked loop circuit (hereinafter referred to as PLL) is used extremely widely as an electronic circuit. As a known document on PLL, Cambridge University Press (CAMBRIDGE UNI
THE ART OP ELECTRONICS by Paul Horowitz and Winfield Hill, published by VER3ITY PRESS
RT OF ELECTRONIC 3) No. 428
I will list the following pages. There, a PLL with a configuration as shown in FIG. 3 is introduced.

In FIG. 3, a phase difference detector (hereinafter referred to as PD) 3
11 is a comparison signal 315 (which is to be compared with the phase φrat of the input signal 313 (frequency f7°), which is a reference signal.
Compare the phase φco+mp of the frequency fcoop),
The phase difference Δφ (=φ, , f~φ..1) is detected. Holding period τ and voltage amplitude width V according to this phase difference Δφ
, the pulse signal 317 having the following is converted by the next stage low-pass filter 319 into a DC signal 321 having the DC voltage V, (oc ■, ·τ·f), and the pulse signal 317 having the voltage controlled oscillator (
(hereinafter referred to as VCO) 323. This VCO
323 generates an output signal 325 having a frequency f0□ proportional to the voltage ■2, which is divided by the frequency divider 327 into
A frequency-divided signal 315 with a frequency f co □ that is downsized to /n is generated and supplied to the PD 311 .

With such a closed loop, VC is adjusted so that Δφ becomes zero.
O323 output frequency f. ut is variably controlled so that when locked, a stable frequency output signal 325 of fo□=n'' f rat is obtained.

(Problem to be solved by the invention) However, in such a conventional system, the VCO
The maximum variable range of the voltage V2 of the DC signal 321 supplied to the DC signal 323 is exclusively regulated by the voltage (1).

For example, when the PD 311 is formed of TTL (4044), the amplitude voltage V is only equal to its power supply voltage, for example, +5V. (2) When the C0323 performs appropriate frequency variable operation, a much larger voltage is often required, and there is a problem that phase locking over a wide range cannot be performed.

The present invention was created in view of these points, and is a phase-locked loop circuit (PLL) that is capable of supplying a control voltage over the drive range of a voltage-controlled oscillator even under a low power supply voltage. is intended to provide.

[Means for solving problems]

FIG. 1 is a principle block diagram showing a phase-locked loop circuit according to the present invention.

In FIG. 1, the phase comparison means 117
The third signal 11 corresponds to the phase difference between 1 and the second signal 113.
Outputs 5.

The extraction means (118) extracts the first signal 11 from the third signal 115.
1 reference frequency component signal 119 is extracted.

The boosting means 121 boosts the signal 119 to generate an AC signal 12.
Outputs 0.

The signal conversion means 125 converts the boosted signal 120 into a DC signal 12.
Convert to 3.

Voltage controlled oscillation means 129 generates an output signal 127 with a repetition frequency corresponding to DC signal 123.

Further, a signal corresponding to the output signal 127 is supplied as a first signal 113 to the phase comparison means 117.

Therefore, a phase-locked closed loop is formed as a whole.

[Effect]

A signal 119 is extracted from the third signal 115 corresponding to the phase difference between the first signal 111 and the second signal 113, the signal is boosted, and a DC signal 123 corresponding to the boosted signal 120 is sent to the voltage controlled oscillation means 129. It is now being supplied. Since variable control of the oscillation frequency is performed using the control voltage as a result of boosting in this way, appropriate control can be performed over a wide range even if the circuit system power supply voltage is shifted to a low voltage.

[Embodiment] FIG. 2 shows an embodiment of the present invention. Here, the phase difference detector (PD) 211 compares and detects the phase difference between the input signal 213, which is a reference clock signal of f rar = 64 kHz, and the comparison signal 215 (its frequency is 512 kflz) generated by local oscillation. The phase difference detection signal 217 from the PD 211 is l/16±1/16 (512 ktl
This results in a pulse signal having a pulse holding period in the range (corresponding to the phase 0 to 2π of the z signal).

From the rectangular wave signal obtained in this way, the reference frequency f-
t (=64 kHz) component is taken out by the 54 kHz tank circuit 231.

The output voltage el of this tank circuit 231 is a 54 kHz sine wave signal having an amplitude proportional to the pulse holding period, and this voltage e is transformed into a large voltage e2 by a step-up means of a transformer 233.

The voltage e8 greatly boosted in this way is transferred to the rectifier circuit 2.
35, and the rectified signal 237 is smoothed through a low-pass filter 239 to obtain a DC voltage signal 221.

The VCO 223 is composed of, for example, a varactor diode (variable capacitance diode), and its capacitance is variably controlled according to the DC voltage of the DC voltage signal 221.
Oscillation output frequency f of the output signal 225 of the VCO 223
. ut is controlled.

This output signal 225 is divided into f by a frequency divider 227. ut
/32, and the frequency-divided signal is supplied as a comparison signal 215 to the PD 211.

In this way, the entire PLL is configured, and by boosting the reference frequency signal after phase difference detection by the transformer 233, even if the power supply voltage of the PLL is lowered, the voltage controlled oscillation of the VCO 223 can be prevented. Sufficient DC control voltage (signal 22
1) is obtained.

In this embodiment, the output frequency f out when phase lock is applied is 16. It is 384MHz.

In the above-described embodiment, the frequency division ratio by the frequency divider 227 was set to 1/32, but the frequency division ratio is not limited to this, and other frequency division ratios may be used, and the oscillation output according to the frequency division ratio Frequency fa
Needless to say, ML can be obtained. Also, frequency divider 2
27 is not provided, and the output signal 225 of vCO is used as the comparison signal 21.
5 may be applied directly to the PD 211, in which case the PLL locks to the frequency f rat of the input signal 213.
becomes.

〔Effect of the invention〕

As detailed above, according to the present invention, even if the power supply voltage of the PLL is reduced to a low voltage, voltage controlled oscillation can be performed stably over a wide range, and such a circuit whose voltage is being lowered can be used. may be well suited for use in systems. Furthermore, stable control is possible even when the power supply voltage temporarily decreases.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the principle of a phase-locked loop circuit according to the present invention, Fig. 2 is a block diagram showing the configuration of a phase-locked loop circuit according to an embodiment of the present invention, and Fig. 3 is a conventional block diagram. FIG. 2 is a configuration block diagram showing an example. In FIG. 1, 117 is a phase comparison means, 118 is an extraction means, 121 is a boosting means, 125 is a signal conversion means, and 129 is a voltage controlled oscillation means. In Fig. 2, 211 is a phase difference detector (PD), 213 is an input signal, 215 is a comparison signal, 231 is a tank circuit, 233 is a transformer, 223 is a voltage-controlled oscilloscope (VCO), and 227 is a frequency divider. It is. Patent applicant: Fujitsu Limited, Rishi, patent attorney Igeta Sada-＼、゛.

Claims (1)

[Claims] Phase comparison means (
117), extraction means (118) for extracting the reference frequency component signal of the first signal (111) from the third signal (115), and an AC signal (120) which is the boosted output signal (119) of the extraction means (118). ), a signal converting means (125) for converting the AC signal into a DC signal (123), and an output signal (12) having a repetition frequency corresponding to the DC signal.
7), and is configured to supply a signal determined according to the output signal (127) as a second signal (113) to the phase comparison means (117). A phase-locked loop circuit characterized by: