JPS6194580A - Servo circuit - Google Patents

Abstract

PURPOSE:To omit many variable resistors by regulating so that the duty of a phase error signal automatically becomes the prescribed duty at speed shifting time. CONSTITUTION:When a speed shift signal is input, a timing forming circuit 9 resets a counter 14. Thus, the output of a D/A converter 16 becomes zero. After the speed of the motor is switched and the time until a phase error signal is stabilized is elapsed, a control start signal is applied. Thus, a counter 12 counts upward during the high level period of the error signal and downward during the low level period. The counter 14 stepwisely increases its output value, and the duty of the error signal gradually increases. When the output of the counter 12 becomes 50% duty, the counter 14 holds the counted value at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention 1 relates to a servo circuit such as a capstan motor in a VTR (video tape recorder).

(b) Conventional technology A method of forming a control signal as a digital value and processing it digitally is shown in, for example, Japanese Patent Publication No. 5B-41690. However, when the speed is changed, setting of the reference signal at that speed is not considered.

FIG. 1 shows a commonly used reference signal setting circuit. The speed error voltage and phase error voltage applied to terminal (11 (21 VC) are added at point fA1 via resistors (R1) (R2>) and are applied to the positive side terminal of comparator (3).

A reference voltage is applied to the negative terminal of the comparator (3), but this reference voltage must be a value that corresponds to the tape speed (capstan motor speed) K, so it is A volume is available. That is, in the case of a capstan motor, since the speed changes due to switching of recording time, search, etc., it is necessary to switch the reference voltage for each mode. (VRl) is the volume for recording and playback in 2-ring, (VB2) 74β
For recording and playback in I, (VB2) is for rewinding Ishinomaki in β■, rVR4> is for picture search in β summer, (VRs) is for rewinding in βI, (VB2)
is the volume for picture search in β-carbon. The volume (VRs) to (VRs) is connected to the VC, and the switching control signal (selected by S+) is connected to the VC.
J is connected to the negative terminal of the comparator (31) via a resistor (Rs).

(Ra)H is a resistor connected to the output terminal and the negative terminal of the comparator (3). The error voltage applied to the terminal fil f21 is converted into an analog value by the voltage i D/A converter which is a digital value, but the control system works so that the duty of the digital value is 50%. However, when switching the volume, the duty may not reach 50% due to variations in motor characteristics. Therefore, the duty must be adjusted to 50% by adjusting the volume for each mode.

1'M Problems to be Solved by the Invention Therefore, the present invention solves the inconvenience of having to adjust the reference signal setting volume in the control system for each mode.

B) Means for solving the problem: means for changing the duty of the phase error signal to a duty that is distant from the predetermined duty when the speed of the motor is changed; a discriminating means that generates a first signal when the signal is not set and generates a $22 signal when a predetermined duty is reached; and a discriminating means that counts clock pulses in one direction in synchronization with the switching of the speed. means for generating a count output while the first signal is applied, and holding and outputting the count value at that time when the 1g2 signal is applied until the next speed change; Supply means for supplying the reference signal setting circuit of.

←Hakui When the speed of the motor is changed, the duty of the phase error signal becomes a value that deviates from the predetermined value (50%). The output of a counter that counts clock pulses in one direction is applied to a reference signal setting circuit to gradually change the duty t from the shifted value toward a predetermined value. When the duty reaches a predetermined value, the second signal is applied from the determining means to the counter, so the counter stops and holds the current value until the next speed change. In this way, adjustments are automatically made for each mode.

fAl Embodiment In the diagram @1 in which the present invention is implemented, (5) is a klovk pulse input terminal, (6) is an input terminal to which a phase error signal in the form of a PWM wave is applied, (71f81 is a control start signal from the system controller, The speed switching signal is applied to the terminal. (9) is a timing pulse generation circuit. a, O are the first AND gates that take the logical product of the clock pulse (dl (!: first gate pulse tc+); The output is supplied to the clock terminal (CLK) of the first counter (2) constituting the determining means (Ill).

The first counter (12) counts up in the up direction when the phase error signal 4 applied from the input terminal (6) to the up/down terminal (U/D) is at a high level, and counts down in the down direction when it is at a low level. The first counter (2) is reset by the first reset pulse +1))K applied from the timing pulse generating circuit (9).

This reset pulse (bl is generated in synchronization with the positive rise of the phase error signal (al).■ monitors the output of the first counter ■, and when the output becomes zero (the phase error signal This is a detection circuit that outputs the first signal (high level) when the duty is not 50%), and outputs the second signal [low level] when it becomes zero. α41ti second clock pulse? Counts in one direction. The reset pulse (bl'ft) of the first counter (2) is used as the second clock pulse (hl) of the second counter (5). Through 1g2 counter C1
41 clock terminal. Furthermore, the second counter Q
4) When the n'lJ2 clock pulse th+ is no longer input due to the second signal from the determining means, the count value at that time is continued to be held. This holding is carried out by the second counter α4.
will continue until it is reset. The second reset pulse tfl that resets the second counter (1Φ) is generated when the speed switching signal is input to the timing pulse generation circuit (9).
0 is a D/A converter which converts the output of the second counter αa into an analog value. D/A converter with +161
The output of is supplied to the reference signal setting circuit α connected to the negative terminal of the comparator α through the line α71. The reference signal setting circuit αg+ consists of a voltage dividing resistor (R7) (Re) and a resistor (R4) connected between the power supply voltage (10B) and ground.
(R8). When the D/Af converter α converter α force is zero, the reference voltage value obtained by the voltage dividing resistor (R7) (R6) is within the lock range of the servo circuit and the duty of the phase error voltage is 50% or less. shall be selected so that the value is the same. The output of the comparator (3) is applied from a terminal α9 to a capstan motor drive circuit (not shown).

Next, the operation will be explained.

When the operation mode of the VTR is switched by driving the operation button, a speed switching signal is sent from the system controller to the terminal (8) at the point (10) shown in FIG. 2, and the timing pulse generation circuit (9) given to. As a result, a second reset pulse (0) is generated on the output path (2) of the timing pulse generating circuit (9), thereby resetting the second counter α4 #'i and the output of the D/A converter αe becomes zero. After the time (T1) for the motor speed to switch and for the phase error voltage to stabilize has elapsed, a control start signal is given from the system controller to the timing pulse generation circuit (9) through the terminal (7), and as a result, the line A control start signal is given to the detection circuit U through 211. When the second counter I is reset and the output of the f)/A converter (IB+ becomes zero, the reference voltage at the reference signal setting circuit α has a phase error voltage duty of 50%.
The comparator +31K acts to obtain a higher value.

Note that analogized speed error voltage and phase error voltage are always applied to the positive terminal of the comparator (3).

A clock pulse (C1J) is input to the first counter a2 during the high level gate pulse tQ1 period and performs a counting operation.This counting operation is performed during the high level period of the phase error signal (a) applied to the up/down terminal (U/D). Counts in the up direction during the low level period, and in the down direction during the low level period.At the time Ct1 when the control start signal is generated
), the duty of the phase error signal (al is less than 50% and the low level period is long, so the count value is negative.The first counter α2 inputs such a count to the first reset pulse fb+ and the gate. Pulse l(
3] repeatedly at regular intervals. Figure 2+6
17#-j The output of the first counter l is hypothetically shown in analog form. Since the detection circuit outputs the first signal (high level) while the 50% duty is not detected, the second clock pulse (b) is input to the second counter α4. , the output value is increased step by step.As a result, the D/A converter α
The output of e is as shown in FIG. 2 (1). Accordingly, the output of the comparator [3] becomes jl in Fig. 2, and the duty of the phase error signal gradually increases.
- When the tee reaches 50% (fourth counting operation in Figure 2), the second signal (low level) is output from the detection circuit αj.
is output and the second AND gate (151 is rendered non-conductive), so the second clock pulse lhl is not applied to the second counter IK.Therefore, the second counter α41 holds the count value at that time.This count value is D/ It continues to be applied to the reference signal setting circuit Q[D through the A converter α61.In this way, the reference voltage that realizes 50% duty is set.

When switching from this state to another mode, the second counter α
4 is reset and the reference voltage in the switched mode is set by the same operation as described above.

In the above, the predetermined value of the phase error signal is set to a duty ratio of 50
%, it is needless to say that the predetermined value does not have to be 50% and may be set to other values in relation to the control system. Further, when the speed (mode) is changed, the means for forcing the error signal to a specific value apart from the predetermined value is to reset the second counter and supply the output of the second counter to the reference signal setting circuit. However, without being limited to this embodiment, the means may be provided separately from the second counter.

(1-1 Effects of the Invention According to the present invention, there is an effect that the reference signal in each mode is automatically set, which is convenient and can omit a large number of volumes.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of a servo circuit embodying the present invention, and FIG. 2 is an explanatory diagram thereof. FIG. 5 is a circuit diagram of a main part of a conventional servo circuit. (al...phase control signal, (3)...comparator, αto...discrimination means, (14)...second counter, αη...
・Line (supply means), αε...Reference signal setting circuit.

Claims (1)

[Claims] (1) It has a control system that forms a motor phase error signal using a PWM wave and operates so that the PWM wave has a predetermined duty, and the control system is provided with a circuit for setting a reference signal. In the servo circuit, means for setting the duty to a duty different from the predetermined duty when the speed of the motor is changed, and generating a first signal when the PWM wave is input and the duty is not the predetermined duty. a discriminating means for generating a second signal when a predetermined duty is reached; and a clock pulse is counted in one direction in synchronization with the switching of the speed, and counting while the first signal is applied from the discriminating means. means for generating an output and, when the second signal is applied, holding and outputting the count value at that time until the next speed change; supply means for supplying the output of the means to the reference signal setting circuit of the control system; A servo circuit characterized by comprising: