JPS6191752A - マイクロコンピユ−タ - Google Patents

マイクロコンピユ−タ

Info

Publication number
JPS6191752A
JPS6191752A JP59212851A JP21285184A JPS6191752A JP S6191752 A JPS6191752 A JP S6191752A JP 59212851 A JP59212851 A JP 59212851A JP 21285184 A JP21285184 A JP 21285184A JP S6191752 A JPS6191752 A JP S6191752A
Authority
JP
Japan
Prior art keywords
cpu
bus
microcomputer
control
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59212851A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0431138B2 (https=
Inventor
Keiji Hamazaki
濱崎　啓司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59212851A priority Critical patent/JPS6191752A/ja
Priority to US06/786,519 priority patent/US4807112A/en
Publication of JPS6191752A publication Critical patent/JPS6191752A/ja
Publication of JPH0431138B2 publication Critical patent/JPH0431138B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
JP59212851A 1984-10-11 1984-10-11 マイクロコンピユ−タ Granted JPS6191752A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59212851A JPS6191752A (ja) 1984-10-11 1984-10-11 マイクロコンピユ−タ
US06/786,519 US4807112A (en) 1984-10-11 1985-10-11 Microcomputer with a bus accessible from an external apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59212851A JPS6191752A (ja) 1984-10-11 1984-10-11 マイクロコンピユ−タ

Publications (2)

Publication Number Publication Date
JPS6191752A true JPS6191752A (ja) 1986-05-09
JPH0431138B2 JPH0431138B2 (https=) 1992-05-25

Family

ID=16629368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59212851A Granted JPS6191752A (ja) 1984-10-11 1984-10-11 マイクロコンピユ−タ

Country Status (2)

Country Link
US (1) US4807112A (https=)
JP (1) JPS6191752A (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2559394B2 (ja) * 1987-02-16 1996-12-04 株式会社日立製作所 通信制御装置
US5430853A (en) * 1987-02-26 1995-07-04 Canon Kabushiki Kaisha Update of control parameters of a direct memory access system without use of associated processor
JP2628194B2 (ja) * 1988-07-28 1997-07-09 株式会社日立製作所 データ処理装置
US5199105A (en) * 1988-09-14 1993-03-30 National Semiconductor Corporation Universal asynchronous receiver/transmitter
US5471637A (en) * 1988-12-30 1995-11-28 Intel Corporation Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
US5170481A (en) * 1989-06-19 1992-12-08 International Business Machines Corporation Microprocessor hold and lock circuitry
JPH03126131A (ja) * 1989-10-11 1991-05-29 Nec Corp 中央処理装置の実行速度制御方式
EP0454605A3 (en) * 1990-04-25 1992-04-22 International Business Machines Corporation Bus request device in a direct memory access (dma) system
US5301282A (en) * 1991-10-15 1994-04-05 International Business Machines Corp. Controlling bus allocation using arbitration hold
US5251312A (en) * 1991-12-30 1993-10-05 Sun Microsystems, Inc. Method and apparatus for the prevention of race conditions during dynamic chaining operations
US5577214A (en) * 1992-05-18 1996-11-19 Opti, Inc. Programmable hold delay
US5561819A (en) * 1993-10-29 1996-10-01 Advanced Micro Devices Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller
JP3174211B2 (ja) * 1994-01-25 2001-06-11 富士通株式会社 バッファストレイジのムーブイン制御方法
KR0135904B1 (ko) * 1994-12-30 1998-06-15 김광호 중앙처리장치의 버스 미사용시 전력소모 방지장치 및 그 방법
JPH10134008A (ja) * 1996-11-05 1998-05-22 Mitsubishi Electric Corp 半導体装置およびコンピュータシステム
JP2001117868A (ja) * 1999-10-22 2001-04-27 Oki Electric Ind Co Ltd 集積回路
JP6380795B2 (ja) * 2014-10-15 2018-08-29 日本精機株式会社 車両用表示装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169248A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 入力条件セレクタ付プログラムカウンタ制御方式

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5248440A (en) * 1975-10-15 1977-04-18 Toshiba Corp Memory access control system
JPS55119720A (en) * 1979-03-09 1980-09-13 Tokyo Electric Power Co Inc:The Operation processing unit
US4479179A (en) * 1979-07-30 1984-10-23 International Business Machines Corporation Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
US4481578A (en) * 1982-05-21 1984-11-06 Pitney Bowes Inc. Direct memory access data transfer system for use with plural processors
US4528626A (en) * 1984-03-19 1985-07-09 International Business Machines Corporation Microcomputer system with bus control means for peripheral processing devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169248A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 入力条件セレクタ付プログラムカウンタ制御方式

Also Published As

Publication number Publication date
US4807112A (en) 1989-02-21
JPH0431138B2 (https=) 1992-05-25

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term