JPS6189632A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS6189632A
JPS6189632A JP21167884A JP21167884A JPS6189632A JP S6189632 A JPS6189632 A JP S6189632A JP 21167884 A JP21167884 A JP 21167884A JP 21167884 A JP21167884 A JP 21167884A JP S6189632 A JPS6189632 A JP S6189632A
Authority
JP
Japan
Prior art keywords
resist film
cooling
sensitivity
baking
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21167884A
Other languages
Japanese (ja)
Other versions
JPH061759B2 (en
Inventor
Fumiaki Shigemitsu
重光 文明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21167884A priority Critical patent/JPH061759B2/en
Publication of JPS6189632A publication Critical patent/JPS6189632A/en
Publication of JPH061759B2 publication Critical patent/JPH061759B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE:To stabilize the sensitivity of a resist film and to facilitate the selection of arbitrary conditions of sensitivity by a method wherein the resist film is heated up above a transition temperature by baking after it is exposed, and then the film is cooled down below the transition temperature at a prescribed speed prior to a developing process thereof. CONSTITUTION:Processes of application and prebaking of a resist film are the same with conventional ones, and the cooling of the resist film is conducted after prebaking. This cooling process may be conducted by natural cooling or any other method, and the thermal history thereof is ignored. Next, exposure of the resist film is conducted in the same way as in a conventional process. After the exposure, pre-development baking is applied, and this baking requires only a time taken until the resist film is heated up above a glass transition temperature Tg. After this pre-development baking is ended, cooling is conducted under a speed control. By controlling or selecting this speed of cooling, the sensitivity of the resist film can be controlled or selected. After this cooling process, processes of development, rinsing, etc. are performed in the same way as in a conventional method.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造工程に係り、特にレジストパ
ターンの形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a process for manufacturing a semiconductor device, and particularly to a method for forming a resist pattern.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

超LSIをはじめとする半導体装置の集積度が高まるに
つれて、微細にしてかつ畠精度のパターン形成技術が要
求されている。このため、許容される寸法精度は非常に
厳しいものとなり、再先端分野では6インチマスク或い
は5インチウェハ内で3σ≦0.1μm(但しσはウェ
ハの平均寸法値に対するばらつきを示す)の寸法精度が
要求され始めている。また、量産ラインで使用されるた
めにはマスク間或いはウェハ間での寸法変動を3σ≦0
.15μmに抑えることが必要であり、一方吊産効果を
高めるためには高感度のレジストが必要とされると共に
、使用する露光6A置(エネルギー照射装置)に適合し
た感度にすべくレジスト膜の感度制御が必要となってい
る。
2. Description of the Related Art As the degree of integration of semiconductor devices such as VLSIs increases, there is a need for fine pattern forming techniques with high precision. For this reason, the permissible dimensional accuracy is extremely strict, and in the cutting-edge field, a dimensional accuracy of 3σ≦0.1 μm (where σ indicates the variation with respect to the average wafer dimension value) within a 6-inch mask or 5-inch wafer is required. is beginning to be demanded. In addition, in order to be used on a mass production line, dimensional variations between masks or wafers must be reduced to 3σ≦0.
.. It is necessary to suppress the thickness to 15 μm, and on the other hand, in order to increase the hanging effect, a highly sensitive resist is required, and the sensitivity of the resist film must be adjusted so that the sensitivity is compatible with the 6A exposure setting (energy irradiation device) used. Control is needed.

ところで従来、レジストパターンを形成する場合には、
第5図のフローヂp −1−に示すような方法が採用さ
れている。まず、被処理板(例えばマスク基板)上にリ
ンス1〜を回転塗布法や浸:貞法により塗布する(ステ
ップ100)。次いで、基板上のレジストIlQを所定
の温度(丁b)でオーブン或いは熱板等の加熱手段で加
熱してプリベータを行なう(ステップ101)。次いで
所定時間だけプリベークした後に、レジスト膜を塗布し
た?!Ha理板を常温、常圧中で20〜30分間程度自
然放冷してV温まで冷却する(ステップ102)。次い
で、冷却後の基板上のレジスト膜にそのレジストに応じ
た所定の露光量で露光を行ないくステップ103)、更
に所定の現像処理(ステップ104)およびリンス処理
を施してレジストパターンを形成する。
By the way, conventionally, when forming a resist pattern,
A method as shown in flow p-1- of FIG. 5 is adopted. First, rinses 1 to 1 are applied onto a plate to be processed (for example, a mask substrate) by a spin coating method or a dipping method (step 100). Next, the resist IlQ on the substrate is heated to a predetermined temperature (temperature b) using a heating means such as an oven or a hot plate to perform prebeta (step 101). Then, after prebaking for a predetermined period of time, a resist film was applied. ! The Ha plate is naturally cooled at room temperature and pressure for about 20 to 30 minutes to a temperature of V (step 102). Next, the resist film on the cooled substrate is exposed to light at a predetermined exposure amount depending on the resist (step 103), and is further subjected to predetermined development processing (step 104) and rinsing processing to form a resist pattern.

しかしながら第5図に示した従来方法では、高感度のレ
ジストは解像性が劣るために所望の寸法精度を得ること
が難しく、逆に高解像性を有するレジストは低感度であ
るため量産ラインで必要とする高スルーブツトが得られ
ないという問題があった。また、レジストの感度調整を
同一リンストで行うことがflシ<、露光条件上もプロ
セス」lb制約された条件下でしか使用できず、適切な
条fl下でのレジストパターンを形成することができな
かった。また、プリベーク後の被処理板上のレジスト膜
の感度に差が生じ、高精度のレジストパターンの形成が
困九になるという欠点があった。
However, with the conventional method shown in Figure 5, it is difficult to obtain the desired dimensional accuracy because the high-sensitivity resist has poor resolution, and conversely, the high-resolution resist has low sensitivity, so it is difficult to obtain the desired dimensional accuracy. There was a problem in that the high throughput required for this process could not be obtained. In addition, since it is possible to adjust the sensitivity of the resist using the same rinse, it can only be used under conditions where the exposure conditions and process are restricted, and it is not possible to form a resist pattern under appropriate conditions. There wasn't. Further, there is a drawback that a difference occurs in the sensitivity of the resist film on the plate to be processed after prebaking, making it difficult to form a highly accurate resist pattern.

〔発明の目的〕[Purpose of the invention]

本発明は上記の如き従来技術の欠点を克服するためにな
されたもので、レジスト膜の感度の安定化を図ると共に
任意の感度条件を選択することを容易にし、もって高精
度のレジストパターンを再現性よく形成しうるようにし
たレジストパターンの形成方法を提供するものである。
The present invention was made in order to overcome the drawbacks of the prior art as described above, and it stabilizes the sensitivity of the resist film and makes it easy to select arbitrary sensitivity conditions, thereby reproducing highly accurate resist patterns. The present invention provides a method for forming a resist pattern that can be formed with high quality.

〔発明の概要〕[Summary of the invention]

上記の目的を達成号−るため本発明は、レジスト膜を露
光した後にベーキングによって転移温度以上まで加熱し
、次いで所定の速度でレジスト膜を冷却して転移温度未
満にした後に、レジスト膜の現像処理を行うようにした
レジストパターンの形成方法を提供づるものである。
In order to achieve the above object, the present invention involves heating the resist film to above the transition temperature by baking after exposing the resist film, cooling the resist film at a predetermined rate to below the transition temperature, and then developing the resist film. The present invention provides a method for forming a resist pattern in which processing is performed.

本発明に係る上記の如きリンス1−パターンの形成方法
は、下記の3つの知見にもとづいてなされている。
The method of forming the rinse 1 pattern as described above according to the present invention is based on the following three findings.

第1の知見は、第5図に示す従来方法で・はブリベータ
後にレジスト膜が被覆された被処理数を自然冷却づ−る
ため、例えば被処理板を立置きした場合には、第6図に
示すような異なる温度の等温線T  、T2.−r3 
(T1>T2>T3)が被処理板で生じるということで
ある。ここで、第6図は被処理(反の冷141中にJj
けるある時間の状態を示しており、J′1間経過に伴っ
て刻々と変化する。第6図に図示づ゛る等)1シ線をも
つ被処理板上のレジストIts!を露光、現像処理した
後のリンス1〜パターンの寸法分イbを精密に測定した
結果、寸法分布と温度分布に強い相関llI係があるこ
とがわかった。
The first finding is that in the conventional method shown in FIG. 5, the number of resist films coated with a resist film is naturally cooled after blubberation. Isotherms of different temperatures as shown in T2, T2. -r3
This means that (T1>T2>T3) occurs on the plate to be processed. Here, FIG. 6 shows the processing target (Jj during cooling 141
It shows the state at a certain time, and changes moment by moment as time J′1 passes. The resist on the plate to be processed with one line (such as shown in FIG. As a result of precise measurements of Rinse 1 to pattern dimensions A and B after exposure and development, it was found that there is a strong correlation between the size distribution and temperature distribution.

第2の知見(ま、上記の被処理板の自然放冷時にJ3い
て被処理(νを立置きにした場合の冷IA速度は、第7
r21に示づような冷141曲線へに従う速度で冷月1
される−1一部と、冷U1曲線Bにilう速度で冷却さ
れる下部とが被処理板上で(]二じるということである
The second finding (well, when the above-mentioned plate to be treated is left to cool naturally, the cooling IA speed when the plate to be treated (ν) is placed vertically is the 7th
Cold moon 1 at a speed that follows the cold 141 curve as shown in r21
This means that the -1 part that is cooled and the lower part that is cooled at a rate that corresponds to the cooling U1 curve B are two-fold on the plate to be processed.

第7図に図示する曲線Δで冷JJlされた被処理板上の
レジスト膜部分の感度について調べたところ、第8図に
示す曲線A′のような感度特性を示すことがわかった。
When the sensitivity of the resist film portion on the plate subjected to cold JJI was investigated using the curve Δ shown in FIG. 7, it was found that it exhibited sensitivity characteristics as shown by the curve A' shown in FIG.

同様に第7図に図示する曲1i1Bで冷却された被処理
板上のレジスト膜部分の感度は、第8図に図示する曲線
B′のような感度特イ1を示すことがわかった。これに
より冷却速度と感度特性の間には強い相関関係があり、
これらがパターン寸法の差異を生じさせる原因であるこ
とがわかった。
Similarly, it has been found that the sensitivity of the resist film portion on the plate to be processed cooled by curve 1i1B shown in FIG. 7 exhibits a sensitivity characteristic 1 as shown by curve B' shown in FIG. As a result, there is a strong correlation between cooling rate and sensitivity characteristics.
It has been found that these are the causes of differences in pattern dimensions.

第3の知見は、第5図に示す従来方法のプリベーク、自
然放冷を経たレジスト膜であっても、露光後、現像処理
前に該レジスト膜のガラス転移点温度TOを越える温度
でベークを行なった後、冷却速度を変化させることによ
って感度が大幅に変化させることができるということで
ある。また、プリベークなどの際のレジスト膜に対する
熱聴歴がどのようなものであっても、現像前に改めて上
記のようにTgを越える温度でベークした後、冷加速度
を変化させることによって感度を変化させつるというこ
とがわかった。
The third finding is that even if a resist film has undergone pre-baking and natural cooling in the conventional method shown in Fig. 5, it must be baked at a temperature exceeding the glass transition temperature TO of the resist film after exposure and before development. After that, the sensitivity can be changed significantly by changing the cooling rate. In addition, no matter what the thermal history of the resist film is during pre-baking, the sensitivity can be changed by baking at a temperature exceeding Tg as described above before development, and then changing the cooling acceleration. I found out that it was Setsuru.

以上の事から、第5図に示す従来技術では冷却過程での
冷却速度を制御していないため、冷却条件により感度が
ふらつき、それが高精度のレジストパターンの形成を困
難に;ノでいる原因であることがわかった。
From the above, the conventional technology shown in Figure 5 does not control the cooling rate during the cooling process, so the sensitivity fluctuates depending on the cooling conditions, which makes it difficult to form highly accurate resist patterns. It turned out to be.

〔発明の実施例〕[Embodiments of the invention]

以下、添付図面の第1図乃至第4図を参照して実施例に
もとづき本発明の詳細な説明する。第1図は本発明に係
るレジストパターンの形成方法を説明するフローチャー
トである。レジスト膜の塗布およびプリベークの工程は
第5図に示す従来の工程と同様である(ステップ100
.101>。
Hereinafter, the present invention will be described in detail based on embodiments with reference to FIGS. 1 to 4 of the accompanying drawings. FIG. 1 is a flowchart illustrating a resist pattern forming method according to the present invention. The resist film coating and pre-baking steps are similar to the conventional steps shown in FIG. 5 (step 100).
.. 101>.

プリベークの後にはレジスト膜の冷却がなされるが、こ
の冷部過程は自然放冷その他のいかなる方法によっても
よく、その熱履歴は問われない(ステップ201)。次
いでレジスト膜の露光が行なわれるが、この工程も第5
図の・従来工程と同様である(ステップ103)。  
  □ 露光の後に本発明の第1の特徴である現像前べ一りがな
される(ステップ202)。このベークに要する時間は
、レジスト1賛のガラス転移温度TOを越えるまでの時
間で十分である。例えばポジ型の電子線感応レジストポ
リ(メチルメタクリレート)、ポリ(70ロエチルαク
ロ0アクリレート)の場合には、ベーク時間は5分で充
分であった。
After prebaking, the resist film is cooled, and this cooling process may be performed by natural cooling or any other method, and its thermal history is not critical (step 201). Next, the resist film is exposed to light, and this step is also the fifth step.
This is the same as the conventional process shown in the figure (step 103).
□ After exposure, the first feature of the present invention, which is the pre-development buffing process, is performed (step 202). The time required for this baking is sufficient to exceed the glass transition temperature TO of the resist. For example, in the case of positive electron beam sensitive resists poly(methyl methacrylate) and poly(70 loethyl α-chloroacrylate), a baking time of 5 minutes was sufficient.

この現像前ベークの後に本発明の第2の特徴である速度
制御された冷却がなされる(ステップ203)。この冷
却速度を制御しあるいは選択することによって、レジス
ト膜の感度を制御あるいは選択することができる。この
冷却工程の後には従来方法と同様にして現像処理(ステ
ップ104)リンス処理等がなされる。
This pre-development bake is followed by rate-controlled cooling, which is the second feature of the present invention (step 203). By controlling or selecting this cooling rate, the sensitivity of the resist film can be controlled or selected. After this cooling step, development processing (step 104), rinsing processing, etc. are performed in the same manner as in the conventional method.

次に添付図面の第2@および第3図を参照して、第1図
に示す本発明方法を実現する加熱冷却装置の一例を説明
する。
Next, with reference to FIGS. 2 and 3 of the accompanying drawings, an example of a heating and cooling apparatus for realizing the method of the present invention shown in FIG. 1 will be described.

第2図は本発明の一実施例に係るレジストパターンの形
成工程に用いられる加熱冷却装置の概略図であり、第3
図は第2因に示す装置の要部拡大断面図である。底部を
除く壁体が断熱材料で形成されたチャンバ1の底部には
薄いガラス板2が設けられている。このチャンバ1内の
土壁には冷却媒体(例えば水)が流通する偏平状の中空
体3が水平に配設されており、この中空体3の両端は冷
却配管4a; 4bを介して冷却流体リザーバ5に連結
されている。入側の冷却配管4aにはポンプ6が介装さ
れている。また、中空体3の下面には吸収率〜9′0%
の酸化アルミニウムからなる受熱板7が水平に設けられ
ている。更に、チャンバ1の左側壁にはバルブ81を介
装したリーク用配管9が連結されており、チャンバ1の
右側壁にはバルブ8□を介装した吸引配管10が3g!
枯されている。この吸引配管10の他端は真空ポンプ1
1に連結されている。チャンバ1底部のガラス板2には
上下動可能でガラス板2と密接乃至11間するホットプ
レート12が配設されている。
FIG. 2 is a schematic diagram of a heating and cooling device used in the resist pattern forming process according to an embodiment of the present invention;
The figure is an enlarged sectional view of the main part of the device shown in the second factor. A thin glass plate 2 is provided at the bottom of a chamber 1 whose walls except the bottom are made of a heat insulating material. A flat hollow body 3 through which a cooling medium (for example, water) flows is horizontally arranged on the earthen wall of the chamber 1, and both ends of this hollow body 3 are connected to the cooling fluid through cooling pipes 4a and 4b. It is connected to the reservoir 5. A pump 6 is installed in the cooling pipe 4a on the inlet side. In addition, the lower surface of the hollow body 3 has an absorption rate of ~9'0%.
A heat receiving plate 7 made of aluminum oxide is provided horizontally. Furthermore, a leak pipe 9 with a valve 81 interposed therein is connected to the left side wall of the chamber 1, and a suction pipe 10 with a valve 8□ interposed on the right side wall of the chamber 1 has a weight of 3 g!
It is withered. The other end of this suction pipe 10 is a vacuum pump 1
1. A hot plate 12 is disposed on the glass plate 2 at the bottom of the chamber 1 and is movable up and down and in close contact with the glass plate 2.

次に、第2図および第3図に示す加熱冷却装置を用いて
レジストパターンを形成する方法を具体的に説明する。
Next, a method of forming a resist pattern using the heating and cooling apparatus shown in FIGS. 2 and 3 will be specifically described.

まず、ブランクマスク上にガラス転移温度(T O’ 
)崎100℃のE8レジスト(ポリメチルメタクリレー
ト)を回転塗布して厚さ0.6μmrLのレジスト膜を
形成する(レジスト塗布)。その後、180℃で1時1
80?度オーブン等によ・リブリベークし、室温まで冷
却する。なお、露光工程の後には現像前べ=り、温度コ
ントロール付冷却工程が用意されているので、この冷I
J1過程は前述のようにいかなる方法によるものであっ
てもよい。
First, the glass transition temperature (T O'
) E8 resist (polymethyl methacrylate) at 100° C. is spin-coated to form a resist film with a thickness of 0.6 μm (resist coating). After that, it was heated to 180℃ for 1 hour and 1 hour.
80? Bake in an oven at 30 degrees and cool to room temperature. Note that after the exposure process, there is a pre-development buffing process and a cooling process with temperature control.
The J1 process may be performed in any manner as described above.

その後、所定のパターンを電子線露光でH^く。After that, a predetermined pattern is exposed to electron beam.

次いで、第2図及び第3図に示1°如くブランクマスク
13を該マスクと同材質のカセット14に収容し、その
状態で/Jセット14をブーヤンバ1のガラス板上にレ
ジスト19が上面側となるように水平にセクトする。次
いで、バルブ81を閉じてバルブ82を開き、真空ポン
プ11を作動してチャンバ1内のガスを排気して真空!
5を10−’torr程度とした後、ポットプレート1
2のヒータを加熱してブランクマスク13上のレジスト
膜を180°Cで5分間ベークする(現象前ベーク)。
Next, the blank mask 13 is housed in a cassette 14 made of the same material as that of the blank mask 13 as shown in FIG. 2 and FIG. Sect horizontally so that Next, the valve 81 is closed, the valve 82 is opened, and the vacuum pump 11 is activated to exhaust the gas in the chamber 1 to create a vacuum!
5 to about 10-'torr, then pot plate 1
The resist film on the blank mask 13 is baked at 180° C. for 5 minutes by heating the heater No. 2 (pre-phenomenon baking).

現象前ベーク終了後、直ちにホットプレー1・12を下
方に移動させてガラス板2に対して離間させ!ζ後、ポ
ンプ6を作動して冷却流体リザーバ5内の水を冷却配管
4a、中空体3、冷却配管4bを通して循環させて、中
空体3下面の受熱板7を十分に冷却する。この時、チャ
ンバ1内(よ高真空状態に保たれているICめ、受熱板
7による放射熱伝達のみでブランクマスク13上のリン
ス1〜B9が均一に所定の速度で冷却される。ブランク
マスク13上のレジスト膜の表面温度がそのTOより低
くなった時に、バルブ81を問いてリーク用配管9を通
してN2ガスを10分間程度供給した後、カセット14
と共にブランクマスク13をチャンバ1から取り出す。
Immediately after the pre-phenomenal baking is completed, hot plates 1 and 12 are moved downward and separated from glass plate 2! After ζ, the pump 6 is operated to circulate the water in the cooling fluid reservoir 5 through the cooling pipe 4a, the hollow body 3, and the cooling pipe 4b, thereby sufficiently cooling the heat receiving plate 7 on the lower surface of the hollow body 3. At this time, the rinses 1 to B9 on the blank mask 13 are uniformly cooled at a predetermined rate only by radiant heat transfer by the heat receiving plate 7 inside the chamber 1 (the IC is kept in a high vacuum state.Blank mask When the surface temperature of the resist film on the cassette 13 becomes lower than its TO, after turning on the valve 81 and supplying N2 gas through the leak pipe 9 for about 10 minutes, the cassette 14
At the same time, the blank mask 13 is taken out from the chamber 1.

次いで、MIBK現像液(液温25℃)で13分間現像
処理を行い[AAリンス液(P&温25°C)での30
秒間のリンス処理を施してブランクマスク上にレジスト
パターンを形成する。なお上記の現咎処理にあたっては
、現像前ベーク後の冷却工程で冷却速度によってコント
ロールされたレジストパターンの感度に応じて現像条件
(現像液cJ磨・温度等)を選択するようにづ−る。
Next, development was carried out for 13 minutes with MIBK developer (solution temperature 25°C) [30 minutes with AA rinse solution (P & temperature 25°C)].
A resist pattern is formed on the blank mask by performing a rinsing process for seconds. In the above-mentioned development process, the development conditions (developing solution CJ polishing, temperature, etc.) are selected according to the sensitivity of the resist pattern, which is controlled by the cooling rate in the cooling step after the pre-development bake.

このようにして上記の加熱冷却装置によりレジスト膜の
描画接に現像前ベーク、均一冷却を施した場合には、ブ
ランクマスクの面内での感1臭均−化により目的とづる
高fi′IIIのリンス1−パターンを形成することが
できる。また現像前ベータの後の冷却速度を制御−する
ことによって、所望の感度のレジストパターンをVlて
、現像条件を感度に合わせて適当に選ぶことにJ:り現
像時間を大幅に短縮することができる。
In this way, when the above-mentioned heating and cooling device performs pre-development baking and uniform cooling on the drawing contact of the resist film, the desired high fi' Rinse 1-pattern can be formed. In addition, by controlling the cooling rate after the pre-development beta, it is possible to obtain a resist pattern with the desired sensitivity and to appropriately select the development conditions according to the sensitivity, thereby greatly shortening the development time. can.

なお上記の実施例において、受熱板として吸収率の異な
る材料を用いて放射熱伝達のみでブランクマスク上のレ
ジスト膜の均一冷却を行なうことによって、感度の安定
化と共に、レジスト膜の感度を8μC/ cm〜0.5
μC/ cmの範囲で変化させることができる。
In the above example, by using materials with different absorption rates as the heat receiving plate and uniformly cooling the resist film on the blank mask only by radiant heat transfer, the sensitivity was stabilized and the sensitivity of the resist film was increased to 8 μC/ cm~0.5
It can be varied in the range of μC/cm.

上記実施例では冷fJI流体すプーバ内の冷却媒体とし
て水を用いたが、この代りに他の冷却液体、或いは冷却
した窒素ガス、アルゴンガス又はフロンガス等を用いて
もよい。
In the above embodiment, water is used as the cooling medium in the cold fJI fluid pool, but other cooling liquids, or cooled nitrogen gas, argon gas, or chlorofluorocarbon gas may be used instead.

また、本発明方法は第2図及び第3図に図示する加熱冷
却装置を用いて現像前ベーク、速度制御付均一冷却を行
なう場合に限定されない、、例えば第4図に示す如く、
底部に搬送ベルト15が配置された偏平型のチャンバ1
′内の上部に受熱板7を水平に配置し、チャンバ1′内
にカセッ1−14と共にセットしたブランクマスク13
表面のレジスト膜と受熱板7との距11fltdが7m
以下と近接して配置できるような構造の加熱冷却装置を
用いてもよい。
Furthermore, the method of the present invention is not limited to the case where pre-development baking and speed-controlled uniform cooling are performed using the heating and cooling apparatus shown in FIGS. 2 and 3. For example, as shown in FIG. 4,
A flat chamber 1 with a conveyor belt 15 arranged at the bottom
The heat receiving plate 7 is arranged horizontally in the upper part of the chamber 1', and the blank mask 13 is set together with the cassette 1-14 in the chamber 1'.
The distance 11fltd between the resist film on the surface and the heat receiving plate 7 is 7 m.
A heating/cooling device having a structure that allows it to be placed in close proximity to the following may be used.

このJ:うな加熱冷却装置より、カセット14のブラン
クマスク13のレジスト膜をホットプレート12による
加熱によって現像前ベークし、ホットプレート12を下
方に移動させた後、中空体3内に水を流通させて受熱板
7を冷却すれば、プリベークされたブランクマスク13
上レジスト膜は受熱(f 7に対して7 mm以下と著
しく近接して配置されているため、チャンバ内を高真空
状態にしたのと同様、放射熱伝達のみでレジスト膜が冷
fdlされ、その結果均−冷u1がなされる。従って、
第4図に図示り”る装置では、チャンバ1′内を高真空
にするための真空ポンプを付設せずに均一冷却を行なう
ことができるという利点がある。
Using this J: UNA heating and cooling device, the resist film on the blank mask 13 of the cassette 14 is heated by the hot plate 12 to bake it before development, and after moving the hot plate 12 downward, water is made to flow inside the hollow body 3. When the heat receiving plate 7 is cooled, the prebaked blank mask 13 is
Since the upper resist film is placed extremely close to the heat receiving layer (less than 7 mm from f7), the resist film is cooled by radiation heat transfer only, similar to when the chamber is in a high vacuum state, and its As a result, uniform cooling u1 is achieved.Therefore,
The apparatus shown in FIG. 4 has the advantage that uniform cooling can be achieved without the need for a vacuum pump to create a high vacuum in the chamber 1'.

〔発明の効果〕〔Effect of the invention〕

上記の如く本発明(・は、レジスト膜を露光した後にベ
ーキングによってガラス転移温度以上まで加熱し、次い
で所定の速度で均一にレジストlI9を冷却してガラス
転移温度未満にした後に、レジスト膜の現像処理を行う
ようにしたので、レジスト膜の感度の安定化を図ると共
に任意の感度条件を選択することを容易にし、もって高
精度のレジストパターンを再現性よく形成しうるように
しjこレジストパターンの形成方法を得ることができる
As described above, in the present invention, after the resist film is exposed, the resist film is heated to a temperature higher than the glass transition temperature by baking, and then the resist film is cooled uniformly at a predetermined rate to below the glass transition temperature, and then the resist film is developed. This process not only stabilizes the sensitivity of the resist film but also makes it easy to select arbitrary sensitivity conditions, thereby making it possible to form highly accurate resist patterns with good reproducibility. A forming method can be obtained.

また、本発明では、現像前ベーク後の冷!Jl工程にお
ける冷却速度を上げることによりレジストの増感効果を
秦づ−ることかできるので、現像時間を大幅に短縮して
スルーブツトの低下を抑えることができる。さらに本発
明では、現像前のベークをすることによってそれ以前の
レジスト膜の熱腰歴を無視できので、プリベーク後の冷
却、露光あるいは環境条件に起因するレジス1−面内の
感度のばらつきを除去し、高精度のレジストパターンを
形成することができる。
In addition, in the present invention, cooling after baking before development! Since the sensitizing effect of the resist can be reduced by increasing the cooling rate in the Jl step, the development time can be significantly shortened and a decrease in throughput can be suppressed. Furthermore, in the present invention, by baking before development, the thermal history of the resist film can be ignored, so variations in sensitivity within the resist 1 plane due to cooling after prebaking, exposure, or environmental conditions are eliminated. Therefore, a highly accurate resist pattern can be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法の工程を説明するフローチャート、
第2図は本発明の一実施例を実現するための加熱冷却装
置の一例の概略図、第3図は第2図に示す装置の要部を
拡大した断面図、第4図は本発明の一実施例を実現する
ための加熱冷却装置の他の例の要部の断面図、第5図は
従来方法の工程を説明するフローチャート、第6図はプ
リベーク後の被処理板を立置きにして自然放冷した時の
温度等方線の説明図、第7図はプリベーク後の被処理板
を立置きにして自然放冷した時の冷却過程を示す特性図
、第8図は第7図に図示した異なる冷却過程のレジスト
部分における露光ωと膜厚残存率のa係を示す特性図で
ある。 1.1′・・・ヂ↑!ンバ、3・・・鍋平状の中空体、
5・・・冷却流量リリ“−バ、7・・・受熱叛、11・
・・真空ポンプ、12・・・ホットプレート、13・・
・ブランクマスク、14・・・カセット、15・・・搬
送ベルト。 出願人代理人  猪  股    清 第2図 ・帛8図     5弓 間 (分) 露 世 量 ′、;’om’、! lC12−
FIG. 1 is a flowchart explaining the steps of the method of the present invention;
FIG. 2 is a schematic diagram of an example of a heating and cooling device for realizing an embodiment of the present invention, FIG. 3 is an enlarged sectional view of the main part of the device shown in FIG. 2, and FIG. A cross-sectional view of the main parts of another example of a heating and cooling device for realizing one embodiment, FIG. 5 is a flowchart explaining the steps of the conventional method, and FIG. Figure 7 is an explanatory diagram of temperature isotropic lines when left to cool naturally. Figure 7 is a characteristic diagram showing the cooling process when the plate to be treated after pre-baking is placed vertically and left to cool naturally. Figure 8 is Figure 7. FIG. 6 is a characteristic diagram showing the relationship between the exposure ω and the a ratio of the film thickness remaining rate in the resist portions in the illustrated different cooling processes. 1.1'...ヂ↑! 3... Hollow body in the shape of a pot,
5... Cooling flow rate reliever, 7... Heat receiving unit, 11.
...Vacuum pump, 12...Hot plate, 13...
-Blank mask, 14...cassette, 15...transport belt. Applicant's agent Kiyoshi Inomata Figure 2, Figure 8 5 minutes (minutes) 'om',! lC12-

Claims (1)

【特許請求の範囲】 1、基板上にレジスト膜を塗布形成してベーキングをす
る第1の工程と、所定波長域の電磁波あるいは所定エネ
ルギーの粒子線を前記レジスト膜に選択的に照射して露
光する第2の工程と、ベーキングによつて前記レジスト
膜を転移温度以上に加熱する第3の工程と、前記レジス
ト膜を転移温度未満の温度まで所定の速度で冷却する第
4の工程と、冷却後の前記レジスト膜を現像処理する第
5の工程とを備えるレジストパターンの形成方法。 2、前記第4の工程におけるレジスト膜の冷却は放射熱
伝達により行うようにした特許請求の範囲第1項記載の
レジストパターンの形成方法。
[Claims] 1. A first step of coating and forming a resist film on a substrate and baking it, and exposing the resist film by selectively irradiating the resist film with electromagnetic waves in a predetermined wavelength range or particle beams with a predetermined energy. a second step of heating the resist film above the transition temperature by baking; a fourth step of cooling the resist film at a predetermined rate to a temperature below the transition temperature; and a fourth step of cooling the resist film to a temperature below the transition temperature. and a subsequent fifth step of developing the resist film. 2. The method of forming a resist pattern according to claim 1, wherein cooling of the resist film in the fourth step is performed by radiant heat transfer.
JP21167884A 1984-10-09 1984-10-09 Method of forming resist pattern Expired - Lifetime JPH061759B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21167884A JPH061759B2 (en) 1984-10-09 1984-10-09 Method of forming resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21167884A JPH061759B2 (en) 1984-10-09 1984-10-09 Method of forming resist pattern

Publications (2)

Publication Number Publication Date
JPS6189632A true JPS6189632A (en) 1986-05-07
JPH061759B2 JPH061759B2 (en) 1994-01-05

Family

ID=16609774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21167884A Expired - Lifetime JPH061759B2 (en) 1984-10-09 1984-10-09 Method of forming resist pattern

Country Status (1)

Country Link
JP (1) JPH061759B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0255360A (en) * 1988-08-22 1990-02-23 Tokyo Electron Ltd Regist processor
JPH02106758A (en) * 1988-10-14 1990-04-18 Matsushita Electric Ind Co Ltd Pattern forming method
US6450803B2 (en) 1998-01-12 2002-09-17 Tokyo Electron Limited Heat treatment apparatus
WO2004090951A1 (en) * 2003-04-01 2004-10-21 Tokyo Electron Limited Heat treating apparatus and heat treating method
KR100543570B1 (en) * 1998-08-05 2006-01-20 동경 엘렉트론 주식회사 Substrate treating method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546559A (en) * 1978-09-29 1980-04-01 Fujitsu Ltd Method of fabricating semiconductor device
JPS5614975A (en) * 1979-07-17 1981-02-13 Rhythm Watch Co Ltd Driving circuit of clock motor
JPS56100417A (en) * 1980-01-16 1981-08-12 Fujitsu Ltd Forming method for resist pattern
JPS58224079A (en) * 1982-06-23 1983-12-26 Ishikawajima Harima Heavy Ind Co Ltd Device for welding membrane to inside circumferential wall of tank
JPS58224078A (en) * 1982-06-23 1983-12-26 Matsushita Electric Ind Co Ltd Arc welding machine
JPS5933585A (en) * 1982-08-19 1984-02-23 Fujitsu Ltd Tablet type input system
JPS59104127A (en) * 1982-12-07 1984-06-15 Nippon Telegr & Teleph Corp <Ntt> Formation of fine pattern

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546559A (en) * 1978-09-29 1980-04-01 Fujitsu Ltd Method of fabricating semiconductor device
JPS5614975A (en) * 1979-07-17 1981-02-13 Rhythm Watch Co Ltd Driving circuit of clock motor
JPS56100417A (en) * 1980-01-16 1981-08-12 Fujitsu Ltd Forming method for resist pattern
JPS58224079A (en) * 1982-06-23 1983-12-26 Ishikawajima Harima Heavy Ind Co Ltd Device for welding membrane to inside circumferential wall of tank
JPS58224078A (en) * 1982-06-23 1983-12-26 Matsushita Electric Ind Co Ltd Arc welding machine
JPS5933585A (en) * 1982-08-19 1984-02-23 Fujitsu Ltd Tablet type input system
JPS59104127A (en) * 1982-12-07 1984-06-15 Nippon Telegr & Teleph Corp <Ntt> Formation of fine pattern

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0255360A (en) * 1988-08-22 1990-02-23 Tokyo Electron Ltd Regist processor
JPH02106758A (en) * 1988-10-14 1990-04-18 Matsushita Electric Ind Co Ltd Pattern forming method
US6450803B2 (en) 1998-01-12 2002-09-17 Tokyo Electron Limited Heat treatment apparatus
KR100543570B1 (en) * 1998-08-05 2006-01-20 동경 엘렉트론 주식회사 Substrate treating method
WO2004090951A1 (en) * 2003-04-01 2004-10-21 Tokyo Electron Limited Heat treating apparatus and heat treating method
US7601933B2 (en) 2003-04-01 2009-10-13 Tokyo Electron Limited Heat processing apparatus and heat processing method

Also Published As

Publication number Publication date
JPH061759B2 (en) 1994-01-05

Similar Documents

Publication Publication Date Title
KR860002082B1 (en) Forming method and apparatus of resistor pattern
JPS6381820A (en) Formation of resist pattern
JPS6189632A (en) Formation of resist pattern
JPS6021522A (en) Formation of resist pattern
US4897337A (en) Method and apparatus for forming resist pattern
EP0185366B1 (en) Method of forming resist pattern
JPH0237688B2 (en)
JPS60176236A (en) Resist processing device
JPH0586642B2 (en)
JPS61180438A (en) Treating device for resist
JPH045258B2 (en)
JPH0480531B2 (en)
JPS61156814A (en) Method and apparatus for resist baking
JPS60117626A (en) Forming method of resist pattern and processing device for resist
JPS60263431A (en) Forming method for resist pattern
JPH0241896B2 (en)
JPS60178626A (en) Formation of resist pattern and resist treater
JPS60157225A (en) Resist pattern forming method
JPS6042829A (en) Formation of resist pattern
JPS59132619A (en) Method and apparatus for forming resist pattern
JPS59231813A (en) Resist pattern formation and resist processing apparatus
JPH09330865A (en) Method and unit for heat treating x-ray mask, and method and unit for processing resist
JPS60157224A (en) Resist pattern forming method and resist treating apparatus
JPH0464171B2 (en)
JPS59231814A (en) Resist pattern formation and resist processing apparatus

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term