JPS6188546A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6188546A JPS6188546A JP20923584A JP20923584A JPS6188546A JP S6188546 A JPS6188546 A JP S6188546A JP 20923584 A JP20923584 A JP 20923584A JP 20923584 A JP20923584 A JP 20923584A JP S6188546 A JPS6188546 A JP S6188546A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- hole
- connection
- semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000004020 conductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 241000288673 Chiroptera Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000413 arsenic oxide Inorganic materials 0.000 description 1
- 229960002594 arsenic trioxide Drugs 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- KTTMEOWBIWLMSE-UHFFFAOYSA-N diarsenic trioxide Chemical compound O1[As](O2)O[As]3O[As]1O[As]2O3 KTTMEOWBIWLMSE-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体チップの上に半導体チップを搭載して
なるチップ・オン・チップ（Ｃｈｉｐ ０ｎＣｈｉｐ
）の半導体装置に係り、特に、両チップ間の回路接続構
造に関す。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a chip-on-chip (Chip-on-Chip) in which a semiconductor chip is mounted on a semiconductor chip.
), and particularly relates to a circuit connection structure between both chips.
大規模集留回路（ＬＳＩ）の高機能化、高集積化により
、近年各種殿能の回路を同−ＬＳＩ内に構成する場合が
多くなってきた。例えばＣＭＯ３とＴＴＬ 、またはア
ナログとＣＭＯ５のデジタルなどの構成を有するＬＳＩ
の要求に対し、同一チップ内に構成することは製造工程
上困難である。無理をして強行しても歩留りの点で極め
て不利である。2. Description of the Related Art In recent years, as large-scale integrated circuits (LSIs) have become more sophisticated and highly integrated, circuits with various functions have increasingly been constructed within the same LSI. For example, an LSI with a configuration such as CMO3 and TTL, or analog and CMO5 digital.
In response to this requirement, it is difficult to configure them within the same chip due to the manufacturing process. Even if it is forced, it will be extremely disadvantageous in terms of yield.
従って、回路機能別に独立のチップを用いれば、それぞ
れに最適なプロセスが適用出来、各機能毎の特徴が生か
せることになり、そのため２チツプからなる所謂チップ
・オン・チップのＬＳＩが検討されるようになった。Therefore, if independent chips are used for each circuit function, the optimal process can be applied to each, and the characteristics of each function can be utilized.For this reason, a so-called chip-on-chip LSI consisting of two chips is being considered. Became.
一方、チップの大きさをウェーハレー、ルまで拡大し、
従来複数のＬＳＩで構成されていた回路を１ＬＳＩに構
成する提案も出て来ているが、この際Ｓこもチップ・オ
ン・チップが検討の対象となる。Meanwhile, the size of chips has been expanded to wafer rays,
There are also proposals for configuring circuits that were conventionally composed of multiple LSIs into a single LSI, and in this case, chip-on-chip is the subject of consideration.
これらのチップ・オン・チップにおいて、二つのチップ
間の回路接続が必須事項であり、特に該チップが大型に
なる場合には、該接続部の位置シこ関する制約の少ない
ことが望まれる。In these chip-on-chip devices, a circuit connection between two chips is essential, and especially when the chip becomes large, it is desired that there be fewer restrictions on the position of the connection portion.
〔従来の技術と発明が解決しようとする問題点〕第２図
（Ａ−１）と（Ａ−２）は従来のチップ・オン・チップ
の接続を示した平面図と側断面図である。[Prior art and problems to be solved by the invention] FIGS. 2A-1 and 2A-2 are a plan view and a side sectional view showing a conventional chip-on-chip connection.
同図において、■は上面に図示されない第一の回路を有
する第一の半導体チップ、２は上面に図示されない第二
の回路を有しチップ１の上に搭載される第二の半導体チ
ップ、３．４は第一と第二の回路とを接続するためそれ
ぞれチップ１．２上において第一、第二の回路に設けら
れた接続パット、５は接続パッド３と４とをボンディン
グにより接続する接続ワイヤである。In the figure, ■ is a first semiconductor chip having a first circuit not shown on the top surface, 2 is a second semiconductor chip having a second circuit not shown on the top surface and is mounted on the chip 1, 3 .4 is a connection pad provided on the chip 1.2 for connecting the first and second circuits, and 5 is a connection for connecting the connection pads 3 and 4 by bonding. It's a wire.
この構成のチップ・オン・チップの接続においては、一
般に、接続パッド４はチップ２の周辺部に配置され、こ
れとワイヤボンディングにより接続出来るよう、接続パ
ッド３はチップ２の外周部に配置されている。In a chip-on-chip connection with this configuration, the connection pads 4 are generally arranged at the periphery of the chip 2, and the connection pads 3 are arranged at the outer periphery of the chip 2 so that they can be connected to this by wire bonding. There is.
このことは、接続パット３ないし４の位置を制約するこ
とになり、特にチップ２が大型になる場合、該チップ内
での配線引回しが多くなって面積効率が低下し、然も、
チップ１を常に千ノブ２より大き（せねばならない問題
がある。This restricts the positions of the connection pads 3 and 4, and especially when the chip 2 becomes large, the number of wiring lines within the chip decreases, and the area efficiency decreases.
There is a problem that tip 1 must always be larger than 2 thousand knobs.
上記問題点は、−上面に第一の回路を有する第一の半導
体チップの該主面上に、該第一の半導体チップに対向し
ない一生面に第二の回路を有する第二の半導体チップが
配設され、該第一の回路の接続バンドと該第二の回路の
接続パッドとが、該第二のチップに形成され内面に絶縁
膜を４．：ｉえた貫通孔を通して導体により接続されて
なる本発明の半導体装置によって解決される。The above problem is that - on the main surface of the first semiconductor chip having the first circuit on the upper surface, there is a second semiconductor chip having the second circuit on the surface not facing the first semiconductor chip; 4. A connecting band of the first circuit and a connecting pad of the second circuit are formed on the second chip, and an insulating film is formed on the inner surface. This problem is solved by the semiconductor device of the present invention, which is connected by a conductor through a through hole.
上記構成によれば、従来のワイヤボンディングが除去さ
れるので、互いに接続される前記第一と第二の回路の接
続バットは、該第二のチップの周辺部に配置されなくと
もその位置が各チップの前記主面上において一致してい
ればよいので、該接続パッドの位置に関する制約が従来
より減少する。According to the above configuration, since the conventional wire bonding is removed, the connection bats of the first and second circuits connected to each other can be located at different positions even if they are not arranged on the periphery of the second chip. Since it is sufficient to match the connection pads on the main surface of the chip, there are fewer restrictions on the position of the connection pads than in the past.
このことから、特に該第二のチップが大型である場合、
その内での配線引回しを低；成させて面積効率を上げる
ことが可能になり、然も該第一のチップを該第二のチッ
プより大きくする必要も無（なる。From this, especially when the second chip is large,
It becomes possible to reduce the amount of wiring within the chip and increase the area efficiency, and there is no need to make the first chip larger than the second chip.
なお、前記導体は、前記絶縁膜により該第二〇チップの
当該接続バンド以外の部分と絶縁されるので、該第二の
チップの内部を通しても問題ない。Note that since the conductor is insulated from the portion of the twenty-th chip other than the connection band by the insulating film, there is no problem even if the conductor passes through the inside of the second chip.
以下本発明の一実施例を図により説明する。企図を通し
同一符号は同一対象物を示す。An embodiment of the present invention will be described below with reference to the drawings. The same reference numerals refer to the same objects throughout the design.
第１図（Ａ−１）と（Ａ−２）は本発明によるＣｈｉｐ
０ｎＣｈｉｐの接続を示した平面図と側断面図、第１
図（Ｂ）はその接続部の拡大側断面図である。FIG. 1 (A-1) and (A-2) are Chips according to the present invention.
Plan view and side sectional view showing the connection of 0nChip, 1st
Figure (B) is an enlarged side sectional view of the connecting portion.
第１図（Ａ−１） 、（Ａ−２）のそれぞれは、従来の
接続を示した第２図（Ａ−１） 、（Ａ−２）に対応す
る図である。即ち、１ａはチップ１に対応する第一の半
導体チップ、２ａはチップ２にスＩ応する第二の半導体
デツプ、３ａ、４ａばそれぞれ接続パソｌ” ３．４に
対応する接続バンドで、５ａは従来の接続ワイヤ５の代
わりをする接続導体である。FIGS. 1(A-1) and (A-2) are diagrams corresponding to FIGS. 2(A-1) and (A-2) showing conventional connections, respectively. That is, 1a is a first semiconductor chip corresponding to chip 1, 2a is a second semiconductor chip corresponding to chip 2, 3a and 4a are connection bands corresponding to the connection terminals 3.4, and 5a is a connection band corresponding to connection path 3.4. is a connecting conductor that replaces the conventional connecting wire 5.
接続ハツト３ａと接続パッド４ａ５よ、チップ２ａをチ
ップ１ａ上に搭載し、た際に互いに接続するパット同、
占が上下方向で一致するように配置されており、チップ
２ａに形成されている貫通孔６を通して接抗導体５ ａ
で接続されている。The connecting hat 3a and the connecting pads 4a5, the same pads that connect to each other when the chip 2a is mounted on the chip 1a,
The contact conductor 5a is arranged so that the top and bottom lines are the same in the vertical direction, and the contact conductor 5a is inserted through the through hole 6 formed in the chip 2a.
connected with.
この接続部の詳細は第１図（Ｂ）の如くである。The details of this connection part are as shown in FIG. 1(B).
チップｌａにおける図示されない第一の回路に設けられ
た接続パッド３ａは、例えばアルミニウム（Ａｌ）上に
チタン（Ｔｉ）などのハリャメクルが被着されてなり、
半導体基板１ｂの上にある絶縁膜ｌｃ上に形成されて、
チップ２ａとの間を絶縁する絶縁膜１ｄシこ周辺部が覆
われている。The connection pads 3a provided in the first circuit (not shown) in the chip la are made of, for example, aluminum (Al) coated with a material such as titanium (Ti).
Formed on the insulating film lc on the semiconductor substrate 1b,
The periphery of an insulating film 1d that insulates between the chip 2a and the chip 2a is covered.
チップ２ａは、接続パッド３ａめ露出部に対応ず・ジ位
置に貫通孔６が形成され、図示されない第二の回路に設
けられた接続パッド４ａは、接続パッド３ａと同様に例
えばＡｌ上にＴｉなどのハリャメクルが技着されてなり
、貫通孔６部に開孔４ｂを設シＪて半・４体栽ｉ２ｂの
上にある絶１ｈ ｈ ２ｃ上に形成されてい・５゜貫通
孔６は、基板２ｂに予め明けられた下孔６ｄと下孔６ａ
の内面に被着された絶縁ＩＱ ６１）とからなり、その
内径は凡そφ５０〜１００μｍである。下孔６ａは、例
えばレーザ光照射またはエツチングなどの方法によって
形成可能である。絶縁ＩＱ６ｂは、絶紹、け２ｃと同じ
く例えばルー珪酸ガラス（ＰＳＧ）または二酸１′ヒシ
リコン（ＳｉＯ２）などからなり、厚さが凡そ１μｍ程
度で、例えばＣＶＤ法により絶縁ＩＩＱ２ｃと一緒に形
成されたものである。The chip 2a has a through hole 6 formed at a position corresponding to the exposed portion of the connection pad 3a, and the connection pad 4a provided in the second circuit (not shown) is made of, for example, Ti on Al, like the connection pad 3a. A hole 4b is formed in the 6th part of the through-hole, and the 5° through-hole 6 is A pilot hole 6d and a pilot hole 6a pre-drilled in the substrate 2b
The inner diameter is approximately φ50 to 100 μm. The pilot hole 6a can be formed, for example, by laser beam irradiation or etching. The insulation IQ6b is made of, for example, silicic acid glass (PSG) or 1' arsenic oxide (SiO2), etc., like the insulation IIQ2c, and has a thickness of approximately 1 μm, and is formed together with the insulation IIQ2c by, for example, the CVD method. It is something that
接続導体５ａは、例えばはんだからなり、チップ１ａ上
にチップ２ａを重ねた後、該はんだのプリフォームを貫
通孔６上に載せ加熱して貫通孔６内に流入させ、接続パ
ッド３ａと接続パッド４ａとを接続させたものである。The connection conductor 5a is made of, for example, solder, and after stacking the chip 2a on the chip 1a, a preform of the solder is placed on the through hole 6 and heated to flow into the through hole 6, thereby connecting the connection pad 3a and the connection pad. 4a are connected.
該はんだは前記バリヤメタルに良く馴染むので、両パッ
ド間の接続は確実なものである。Since the solder blends well with the barrier metal, the connection between both pads is reliable.
かくして、チップ１ａとチップ２ａとの間の回路接続が
形成される。A circuit connection between chip 1a and chip 2a is thus formed.
以上説明したように、本発明の構成によれば、チ・７プ
・オン・チップの半導体装置における両チップ間の回路
接続部の位置に関する制約を従来より減少させることが
出来て、特に上側チップが大型である場合、その内での
配線引回しを低減させて面積効率を上げることが可能に
なり、然も下側チップを上側チップより大きくする必要
も無くなる効果がある。As explained above, according to the configuration of the present invention, it is possible to reduce restrictions regarding the position of the circuit connection between both chips in a chip-on-chip semiconductor device compared to the conventional one, and in particular, it is possible to If the chip is large, it is possible to reduce wiring routing within the chip and increase area efficiency, and there is also an effect that it is not necessary to make the lower chip larger than the upper chip.
図面において、
第１図（Ａ４）と（Ａ−２）は本発明によるチップ・オ
ン・チップの接続を示した平面図と側断面図、
第１図（Ｂ）はその接続部の拡大側断面図、第２図（Ａ
−１）と（Ａ−２）は従来のチップ・オン・チップの接
続を示した平面図と側断面図である。
図中において、
１．１ａ、２．２ａは
半導体チップ、 １ｂ、２ｂは基板、
１ｃ、１ｄ、２ｃは絶縁膜、 ３．３ａ、４．４ａは
接続パッド、
４ｂは４ａの開孔、 ５は接続ワイヤ、５ａは
接続導体、 ６は貫通孔、６ａは６の下孔、
６ｂは６の絶縁膜、を’ｃｈ（’ｈ示Ｊ−・
ｅ剥ニー］ｊ）代理人 弁
理士 松岡宏四部−釜コ・１山阻５In the drawings, Fig. 1 (A4) and (A-2) are a plan view and a side sectional view showing the chip-on-chip connection according to the present invention, and Fig. 1 (B) is an enlarged side sectional view of the connection part. Figure, Figure 2 (A
-1) and (A-2) are a plan view and a side sectional view showing a conventional chip-on-chip connection. In the figure, 1.1a and 2.2a are semiconductor chips, 1b and 2b are substrates, 1c, 1d and 2c are insulating films, 3.3a and 4.4a are connection pads, 4b is an opening in 4a, and 5 is connection wire, 5a is a connection conductor, 6 is a through hole, 6a is a pilot hole of 6,
6b is the insulating film of 6, 'ch ('h indicates J-・
e-exfoliation] j) Agent Patent attorney Hiroshi Matsuoka - Kamako 1 Yamaben 5
Claims (1)
主面上に、該第一の半導体チップに対向しない一主面に
第二の回路を有する第二の半導体チップが配設され、該
第一の回路の接続パッドと該第二の回路の接続パッドと
が、該第二のチップに形成され内面に絶縁膜を備えた貫
通孔を通して導体により接続されてなることを特徴とす
る半導体装置。A second semiconductor chip having a second circuit on one main surface not facing the first semiconductor chip is disposed on the main surface of the first semiconductor chip having a first circuit on one main surface. , characterized in that the connection pad of the first circuit and the connection pad of the second circuit are connected by a conductor through a through hole formed in the second chip and having an insulating film on the inner surface. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20923584A JPS6188546A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20923584A JPS6188546A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6188546A true JPS6188546A (en) | 1986-05-06 |
Family
ID=16569592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20923584A Pending JPS6188546A (en) | 1984-10-05 | 1984-10-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6188546A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0198253A (en) * | 1987-10-09 | 1989-04-17 | Sharp Corp | Manufacture of solid type semiconductor device |
| JPH01140753A (en) * | 1987-11-27 | 1989-06-01 | Sharp Corp | Three-dimensional semiconductor device |
| EP1439576A2 (en) | 2003-01-15 | 2004-07-21 | Shinko Electric Industries Co., Ltd. | Through hole manufacturing method |
| US7119428B2 (en) | 2004-03-01 | 2006-10-10 | Hitachi, Ltd. | Semiconductor device |
-
1984
- 1984-10-05 JP JP20923584A patent/JPS6188546A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0198253A (en) * | 1987-10-09 | 1989-04-17 | Sharp Corp | Manufacture of solid type semiconductor device |
| JPH01140753A (en) * | 1987-11-27 | 1989-06-01 | Sharp Corp | Three-dimensional semiconductor device |
| EP1439576A2 (en) | 2003-01-15 | 2004-07-21 | Shinko Electric Industries Co., Ltd. | Through hole manufacturing method |
| US6831000B2 (en) | 2003-01-15 | 2004-12-14 | Shinko Electric Industries Co., Ltd. | Semiconductor device manufacturing method |
| US7119428B2 (en) | 2004-03-01 | 2006-10-10 | Hitachi, Ltd. | Semiconductor device |
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