JPS6187322A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6187322A
JPS6187322A JP19230184A JP19230184A JPS6187322A JP S6187322 A JPS6187322 A JP S6187322A JP 19230184 A JP19230184 A JP 19230184A JP 19230184 A JP19230184 A JP 19230184A JP S6187322 A JPS6187322 A JP S6187322A
Authority
JP
Japan
Prior art keywords
fet
mos
shallow
substrate
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19230184A
Other languages
Japanese (ja)
Other versions
JPH0719759B2 (en
Inventor
Juri Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP59192301A priority Critical patent/JPH0719759B2/en
Priority to US06/756,895 priority patent/US4669176A/en
Publication of JPS6187322A publication Critical patent/JPS6187322A/en
Publication of JPH0719759B2 publication Critical patent/JPH0719759B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Abstract

PURPOSE:To enable the formation of the shallow N type diffused junction layer of a low sheet resistance at low cost by forming an SOPSG on a surface of silicide followed by a heat treatment using a halogen lamp. CONSTITUTION:On a silicon substrate 1, a gate oxide film 8, a polycrystalline silicon gate electrode 10 and a side wall insulating film SiO2 9 are formed. After forming a high-melting point metal or a high-melting point metal layer 11 on the gate electrode and the source and drain selectively, the substrate is coated with an SOPSG12 by a spin coater and the coated substrate is baked and is subjected to a high-temp. and short-time heat treatment by use of a halogen lamp to form a MOS.FET having a shallow N type diffusion layer 13. In this case, the shallow junction reduces a junction capacity and makes switching of the MOS.FET faster and at the same time, it enables miniaturization of the MOS.FET.
JP59192301A 1984-07-30 1984-09-13 Method for manufacturing semiconductor device Expired - Lifetime JPH0719759B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59192301A JPH0719759B2 (en) 1984-09-13 1984-09-13 Method for manufacturing semiconductor device
US06/756,895 US4669176A (en) 1984-07-30 1985-07-19 Method for diffusing a semiconductor substrate through a metal silicide layer by rapid heating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59192301A JPH0719759B2 (en) 1984-09-13 1984-09-13 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6187322A true JPS6187322A (en) 1986-05-02
JPH0719759B2 JPH0719759B2 (en) 1995-03-06

Family

ID=16288995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59192301A Expired - Lifetime JPH0719759B2 (en) 1984-07-30 1984-09-13 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0719759B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308790A (en) * 1992-10-16 1994-05-03 Ncr Corporation Selective sidewall diffusion process using doped SOG
US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP
US5322805A (en) * 1992-10-16 1994-06-21 Ncr Corporation Method for forming a bipolar emitter using doped SOG
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US5340752A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method for forming a bipolar transistor using doped SOG
JPH07183505A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55110036A (en) * 1979-02-19 1980-08-25 Fujitsu Ltd Method for preparation of semiconductor device
JPS58168221A (en) * 1982-03-29 1983-10-04 Toshiba Corp Preparation of semiconductor device
JPS58223320A (en) * 1982-06-22 1983-12-24 Ushio Inc Diffusing method for impurity
JPS59105366A (en) * 1982-12-08 1984-06-18 Oki Electric Ind Co Ltd Manufacture of metal oxide semiconductor type transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55110036A (en) * 1979-02-19 1980-08-25 Fujitsu Ltd Method for preparation of semiconductor device
JPS58168221A (en) * 1982-03-29 1983-10-04 Toshiba Corp Preparation of semiconductor device
JPS58223320A (en) * 1982-06-22 1983-12-24 Ushio Inc Diffusing method for impurity
JPS59105366A (en) * 1982-12-08 1984-06-18 Oki Electric Ind Co Ltd Manufacture of metal oxide semiconductor type transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308790A (en) * 1992-10-16 1994-05-03 Ncr Corporation Selective sidewall diffusion process using doped SOG
US5322805A (en) * 1992-10-16 1994-06-21 Ncr Corporation Method for forming a bipolar emitter using doped SOG
US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US5340752A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method for forming a bipolar transistor using doped SOG
US6010963A (en) * 1992-10-23 2000-01-04 Hyundai Electronics America Global planarization using SOG and CMP
JPH07183505A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0719759B2 (en) 1995-03-06

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term