JPS6186852A - Move-in control system - Google Patents

Abstract

PURPOSE:To improve the efficiency of a move-in action by performing this action including the next block under the prescribed conditions in a first move-in mode. CONSTITUTION:The instruction extracting request given from an instruction executing unit 1 is informed to a storage control part 2 together with an instruc tion access address via a signal line (a). The part 2 indicates the normal 1-block move-in to a move-in control part 3 as long as said extracting request is equal to a BS non-hit. Thus the 1-block data is stored to a buffer memory part 7 from a memory unit 5. While the part 2 transfers two blocks continuously to the part 7 from the unit 5 as long as the extracting request indicates an instruction prefetch access or the extraction of a branch destination instruction and no page cross exists between a designated block and its following block with the intra-block address set within a setting range.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention provides a method for determining whether the address within a block of the access address is within a set range when a desired address does not exist in the buffer memory (cache memory) during instruction fetch access. The present invention relates to a move-in control method in which it is possible to check whether the block to which the access address belongs and the next block are located.

[Prior art and problems]

In a buffer storage type information processing device, when an access address is not registered in the tag (TAG) section of buffer A (BS non-hit) during instruction fetch access or operand access, the block unit containing the access address is The data is transferred to the corresponding buffer storage area. This is called a move-in operation.

As for the move-in execution method, if move-in bypass is not performed, all the moved-in block data is stored in the hasa memory a, and the tag information corresponding to the moved-in block in the buffer memory is validated. After that, the data at the access address that caused the move-in is read from the buffer storage. In addition, when move-in bypass is performed, all the moved-in block data is stored in the buffer memory, and the tag information corresponding to the moved-in block in the buffer memory is enabled, and the moved-in block data The necessary part of the data is sent to the access source during the move-in cause access. Therefore, the move-in bypass method has the advantage of shortening the move-in time.

B in instruction fetch access such as instruction prefetch or branch instruction target access in pipeline control
If S non-hit occurs, and the instruction fetch access address is close to the next block, the next block is also B.
In most cases, BS
Immediately after the move-in of the non-hit block, a move-in operation for the next block is required. In such a case, if the move-in operation is performed including the next block during the first move-in, it is possible to shorten the move-in operation.

[Purpose of the invention]

The present invention is based on the above consideration, and an object of the present invention is to provide a move-in control method that allows move-in operations to be performed efficiently.

[Means to achieve the purpose]

Therefore, in the move-in control method of the present invention, when an instruction fetch request is issued from the instruction execution unit, it is checked whether the corresponding data exists in the buffer storage, and if it does not exist, it is specified in the instruction fetch request. One block or two blocks of data containing the
This is a move-in control method in which the data is read from the unit and moved into the buffer memory, and if the corresponding data does not exist in the buffer memory, the instruction fetch request causes instruction prefetch access or branch destination instruction fetch access. be specified,
There is no page cross between the block containing the data specified in the instruction fetch request and the next block, the address within the block of the instruction access address of the instruction fetch request is within the set range, and the instruction Provided that the block next to the block containing the data specified in the instruction fetch request does not exist in the buffer storage, the block containing the data specified in the instruction fetch request and the next block are sequentially stored in the memory unit. It is characterized in that the data is read from the memory and moved into the buffer storage.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a diagram for explaining the move-in control of the present invention and conventional move-in control, and FIG. 3 is a diagram showing the storage control unit and move-in control shown in FIG. 3 is a flowchart showing processing performed by a control unit.

In FIG. 1, 1 is an instruction execution unit, 2 is a storage control unit, 3 is a move-in control unit, 4 is a memory access controller, 5 is a memory unit, 6 is a buffer storage tag unit, and 7 is a buffer storage tag unit. Data section 8 indicates a multiplexer.

The instruction execution unit 1 makes requests to fetch instructions, requests to fetch operands, requests to store operands, decodes instructions, executes operations, and the like.

An instruction fetch request from the instruction execution unit 1 is notified to the storage control unit 2 along with the instruction 7 access address via the signal line a. In order to know whether the data corresponding to the instruction access address is registered in the buffer storage, the storage control section 2 places the converted instruction access address on the signal yAb and sends it to the tag section 6.
and gives a read instruction to the data section 7 of the buffer storage.

Whether it is a BS hint or a BS non-hit is notified from the tag section 6 to the storage control section 2 via the signal line C.

If BS is hit, data 'frfA h'B
The S read data is now valid, which is sent to multiplexer 8.
is sent to the instruction execution unit 1 via.

When a BS non-hit occurs, if the instruction fetch request from the instruction execution unit 1 is due to instruction prefetch or target access of a branch instruction, the storage control unit 2 uses the instruction access address to detect move-in of the next block. It is checked whether or not the address is within a preset block address range. Note that whether the instruction fetch request is due to instruction prefetch or target access of a branch instruction is indicated by a signal on signal line a. The operation at this time is shown in FIG. In FIG. 2, IAA indicates an instruction access address. In addition, in FIGS. 2A and 2B, the lower row shows the move-in operation of the present invention, and the upper row shows the move-in operation according to the prior art. In this embodiment, the unit of transfer with the 1Pro.7 32-hide memory unit 5 is 8 h bytes. Therefore, to perform block transfer of 32 hides, it is necessary to perform block transfer of 8 hides x 4 times. Further, this embodiment also performs move-in bypass control, and when moving in, 8-byte data including the address of the access source is always moved in first. In this embodiment, the BS
When there is a non-hint and there is no page cross, set the range of addresses in the block that will enable the BS non-hit detection operation for the next book to the range of 8 bytes after the 32-note block address. ing. BS non-hi of the next block within the address range set by the instruction access address IAA.

If the start detection operation is permitted, it is checked by the signal line whether or not the next block is registered in the Hasophat log'LQ. If the result is a BS hint, it instructs the move-in control unit 3 to perform a normal 1-pro Nokpa move-in via the signal line d. When the move-in control unit 3 is activated, a memory access request for one move-in is sent to the memory access controller 4 via the signal line e, and one block read from the memory unit 5 is sent to the memory access controller 4. The data is sent to the no\nofa memory via the signal wire g. When performing a move-in bypass, the signal line 1 causes the multiplexer 8 to output its upper input, and the move-in data on the data line g is sent to the instruction execution unit 1 via the multiplexer 8. When the next block has a BSS non-hit, the storage control section 2 instructs the move-in control section 3 to move in two blocks (64 hides). Then, the two blocks of move-in data read from the memory unit 5 are transferred from the memory access controller 4 consecutively 8 times by 8 times.

FIG. 3 is a flowchart showing move-in processing according to the present invention. These processes are performed by the storage control unit 2 and move-in control unit 3. In FIG. 3, TLB means address translation buffer, DAT means address translation processing, and BS means buffer storage.

■ When there is an access request from instruction execution unit 1,
Access TLB.

■ Check whether it is a TLB hint. If Yes, process ``■'' is performed, and if NO, process ``■'' is performed.

■ Check whether there is an access protection error.

If Yes, process (2) is performed, and if No, process (2) is performed.

■13 Perform S access.

■ Test 8 times to see if it's a BS hint or not. If Yes, process 0 is performed, and if No, process ■ is performed.

■ Check whether it is an instruction fetch access such as an instruction prefetch access or a target access of a branch instruction.

When Yes, process ■ is performed, and when No, process @ is performed.

■ Check whether the address within the block of the instruction access address exists within the set range. When Yes, process ■ is performed, and when NO, process @ is performed.

■ Check whether there is a page cross between the next block and the next block. If Yes, perform the @ process, and if No, perform the ■ process. The page between the next block
If it is a cross, the next block has a different TLB registration entry. Therefore, since there is a possibility that the next block has no TLB hint, a move-in of one block transfer is performed when a page cross occurs.

■ Perform BS access to the next block.

@ Check twice whether it is a BS hit or not.

02 Performs move-in processing for block transfer.

@ Perform move-in processing for 1 block transfer.

@ Perform DAT processing.

■ Check for conversion errors. If Yes, the [phase] process is performed, and if No, the [phase] process is performed.

[Phase] Report an exception. This causes a program interrupt.

[Phase] Register the conversion result in the TLB.

The read data from 013S is sent to the instruction execution unit 1.

[Effects of the Invention] As is clear from the above description, according to the present invention, move-in processing can be performed efficiently, thereby improving the performance of the information processing device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a diagram for explaining the move-in control j111 of the present invention and conventional move-in control, and FIG. 3 is a diagram showing the storage control unit and the conventional move-in control of FIG. 7 is a flowchart showing processing performed by a move-in control unit. DESCRIPTION OF SYMBOLS 1... Instruction execution unit, 2... Storage control unit 3... Move-in control unit, 4... Memory access controller, 5... Memory unit, 6...
Tag section of Hasophah memory, 7... Book of Hasophah 1. Data section of a, 8... multiplexer.

Claims (1)

[Claims] When an instruction fetch request is issued from the instruction execution unit,
Checks whether the corresponding data exists in the buffer memory, and if it does not exist, reads one or two blocks of data containing the data specified in the instruction fetch request from the memory unit and moves it into the buffer memory. If the move-in control method is now used and the corresponding data does not exist in the buffer storage above,
The instruction fetch request specifies instruction prefetch access or branch destination instruction fetch access, and there is no page cross between the block containing the data specified in the instruction fetch request and the next block. , on the condition that the in-block address of the instruction access address of the instruction fetch request is within the set range, and that the block following the block containing the data specified in the instruction fetch request does not exist in the buffer storage, A move-in control method characterized in that a block containing data specified by the instruction fetch request and the next block are successively read from the memory unit and moved into the buffer storage.