JPS6173358A - Case for lsi - Google Patents

Case for lsi

Info

Publication number
JPS6173358A
JPS6173358A JP19498284A JP19498284A JPS6173358A JP S6173358 A JPS6173358 A JP S6173358A JP 19498284 A JP19498284 A JP 19498284A JP 19498284 A JP19498284 A JP 19498284A JP S6173358 A JPS6173358 A JP S6173358A
Authority
JP
Japan
Prior art keywords
lsi
chip
case
power supply
fuses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19498284A
Other languages
Japanese (ja)
Inventor
Katsumi Fujinami
藤浪　克美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19498284A priority Critical patent/JPS6173358A/en
Publication of JPS6173358A publication Critical patent/JPS6173358A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To protect a bonding wire and a LSI chip by interposing a fuse for protection against overcurrents to an electric circuit between a terminal for a power supply or grounding and the LSI chip and annexing the fuse to the outer surface of a case proper. CONSTITUTION:A LSI chip 2 is mounted to a case proper 1, and a plurality of terminals containing terminals 3, 4 for a power supply or grounding are fitted. Electric circuits 5a, 5b tying the chip 2 and the power supply terminal 3 or the grounding terminal 4 are set up into the main body 1. Fusesfor protection against overcurrents are interposed to one parts of the electric circuits 5a, 5b, and fuses 7a, 7b are annexed to one parts of the outer surface of the main body 1. When overcurrents flow through the fuses 7a, 7b in the constitution, the fuses 7a, 7b are fusion-cut by the currents, and the electric circuits 5a, 5b are opened, thus protecting bonding wires 6a, 6b and the chip 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＬＳＩチップを実装するためのケースに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a case for mounting an LSI chip.

〔従来の技術〕[Conventional technology]

従来のＬＳＩチップを実装するケース（儂、ケースに設
けた複数の端子とＬＳＩチップとの間でボンディング線
ヲ用いることによりボンディングした後、その内部にＬ
ＳＩチップを封印、実装するものであるが、該ＬＳＩケ
ースには電源或いは接地の端子に過電流が印加された場
合に、その′あ：流がＬＳＩチンプ或いは前記ボンディ
ング線に直接流れるのｋｌｓｆｌｌＥする機能がなかっ
た。A case in which a conventional LSI chip is mounted (I used bonding wires between the multiple terminals provided on the case and the LSI chip, and then installed an LSI chip inside the case.
The SI chip is sealed and mounted, but if an overcurrent is applied to the power supply or ground terminal of the LSI case, the current will flow directly to the LSI chip or the bonding wire. There was no function.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

そのため、過電流が流れた場合には、ＬＳＩケースを開
封してＬＳＩチップの破壊或いはボンディング線の溶断
を点検し、ボンディングの溶１ｍ事故の場合にはボンデ
ィング線を張り替えなければならず、ＬＳＩチップが破
壊された場合には廃棄するほかなく、経済的な面及びメ
ンテナンスの面で間８位があった。Therefore, if an overcurrent flows, the LSI case must be opened and the LSI chip must be inspected for damage or bonding wires to be fused.If the bonding melts 1m, the bonding wire must be replaced and the LSI chip If it is destroyed, there is no choice but to discard it, which ranked 8th in terms of economy and maintenance.

本発明は前記問題点全解消するもので、ＬＳＩチップの
安全性を向上するようにしたＬＳＩケース士提供するも
のである。The present invention solves all of the above problems and provides an LSI case engineer that improves the safety of LSI chips.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は内部に封印したＬＳＩチップと、該ＬＳＩチッ
プから引き出した、祇諒或いは候地の端子と含む４７　
Ｈの端子とを有するＬＳＩケースにひいて、前記電源或
いは接地の端子と前記ＬＳＩチップとの間の電路に過電
流保護用ヒユーズを介在させ、該ヒユーズ全ケース本体
の外面一部に付設したこと全特徴とするＬＳＩケースで
ある。The present invention includes an LSI chip that is sealed inside and a terminal that is open or closed and that is pulled out from the LSI chip.47
In an LSI case having an H terminal, an overcurrent protection fuse is interposed in the electrical path between the power supply or ground terminal and the LSI chip, and the fuse is attached to a part of the outer surface of the entire case body. This is an LSI case with all the features.

〔実施例〕〔Example〕

以下に、本発明の一実施例を図により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図において、ケース本体１にＨＬＳＩＬＳＩチップ
２され、また電源或いは接地の端子３，４を含む↑型数
の端子を有している。また、ケース本体１内にはＬＳＩ
チップ２と電源端子３或いは接地端子４との間を結ぶ電
路５ａ＋５ｂが内装され、該篭絡５ａ　ｌ　５ｂのＬＳ
Ｉチップ側の端部とＬＳＩチップ２の：ａ源電極或いは
接地電極との間はボンディング線ｂａ＋６ｂにて接続さ
れている。同様に電源端子及び接地端子以外の端子とＬ
ＳＩチップのこれらの端子に７１応する′電極との間は
ボンディング線にてボンティングして接続されている。In FIG. 1, an HLSILSI chip 2 is mounted on a case body 1, and has terminals of ↑ types including terminals 3 and 4 for power supply or ground. In addition, there is an LSI inside the case body 1.
An electric line 5a+5b connecting the chip 2 and the power terminal 3 or the ground terminal 4 is installed inside, and the LS of the cable 5a l 5b
The end on the I chip side and the :a source electrode or ground electrode of the LSI chip 2 are connected by a bonding wire ba+6b. Similarly, terminals other than the power supply terminal and the ground terminal and L
These terminals of the SI chip are connected to electrodes corresponding to 71 by bonding wires.

本発明は、前記電路５ａ、５ｂの一部に過電流保護用ヒ
ユーズ７ａ、７ｂを介装し、該ヒユーズ７ａ、７ｂをケ
ース本体１の外面一部に付設したものである。ヒユーズ
７ａ、７ｂの容量は、ヒユーズの許容電流くボンディン
グ課許容電流とする。In the present invention, fuses 7a and 7b for overcurrent protection are interposed in a part of the electric circuits 5a and 5b, and the fuses 7a and 7b are attached to a part of the outer surface of the case body 1. The capacity of the fuses 7a and 7b is the allowable current of the fuses multiplied by the allowable current of the bonding section.

実施例において、ヒユーズ７ａ、７ｂに過電流が流れる
と、その電流によりヒユーズ７ａ、７ｂが溶断して電路
５　ａ　ｓ　５　ｂを開放することになり、ボンディン
グ線６ａ＋６ｂ及びＬＳＩチック２が保護される。溶断
したＬＳＩケースのヒユーズ７ａ＋７ｂは一目瞭然であ
り、容易に過電流発生の有無を確認でき、また本体１を
開くことなく、外部のヒユーズを交換するだけで再使用
が可能になる。In the embodiment, when an overcurrent flows through the fuses 7a and 7b, the current melts the fuses 7a and 7b, opening the electric circuit 5a and 5b, thereby protecting the bonding wires 6a+6b and the LSI chip 2. . The blown fuses 7a+7b of the LSI case are obvious at a glance, and it is easy to check whether overcurrent has occurred, and the main body 1 can be reused by simply replacing the external fuses without opening it.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、ＬＳＩケースの外観検査
により過電流発生の有無を確認するようにしたため、ケ
ースを開封して内部を検査する手枕を必要とせず、ヒユ
ーズのみを交換することにより再使用することができ、
したがってメンテナンスを簡素化できる。さらに過電流
発生時に、ヒユーズ全浴断して電路を断つため、ＬＳＩ
チックを被嵌から保良できる効果を有するものである。As explained above, the present invention uses an external inspection of the LSI case to confirm the presence or absence of overcurrent, so there is no need to open the case and inspect the inside, and the present invention can be reused by simply replacing the fuse. can be used,
Therefore, maintenance can be simplified. Furthermore, when an overcurrent occurs, the LSI
This has the effect of preventing ticks from becoming stuck.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す一部断面した斜視図で
ある。 １　・ケース本体　　　　２・・・ＬＳＩチップ３・・
電源端子　　　　　４・・接地端子５ａ　ｒ　５ｂ　＝
電路　　　　　７ａ、７ｂ　＋＋＋ヒユーズ特許出願人
　　日本電気株式会社 代理人　弁理士　　菅　　　野　　　　中　　１ニア、
、、。 −・、−。 ／：ケース本体 ２：ｌＳｄチツア ３：電源端子 ４：接地端す 、ｆ４　、ｆｂ　′＠路 ７ａ、ゐ、ヒューズFIG. 1 is a partially sectional perspective view showing an embodiment of the present invention. 1.Case body 2.LSI chip 3..
Power supply terminal 4...Ground terminal 5a r 5b =
Electrical circuit 7a, 7b +++ Hughes patent applicant NEC Corporation agent Patent attorney Kanno Naka 1,
,,. −・、−. /: Case body 2: lSd circuit 3: Power terminal 4: Ground terminal, f4, fb'@Route 7a, ゐ, fuse

Claims (1)

【特許請求の範囲】[Claims] （１）内部に封印したＬＳＩチップと、該ＬＳＩチップ
から引き出した、電源或いは接地の端子を含む複数の端
子とを有するＬＳＩケースにおいて、前記電源或いは接
地の端子と前記ＬＳＩチップとの間の電路に過電流保護
用ヒューズを介在させ、、該ヒューズをケース本体の外
面一部に付設したことを特徴とするＬＳＩケース。(1) In an LSI case that has an LSI chip sealed inside and a plurality of terminals including a power supply or ground terminal drawn out from the LSI chip, an electric path between the power supply or ground terminal and the LSI chip. An LSI case characterized in that an overcurrent protection fuse is interposed in the LSI case, and the fuse is attached to a part of the outer surface of the case body.
JP19498284A 1984-09-18 1984-09-18 Case for lsi Pending JPS6173358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19498284A JPS6173358A (en) 1984-09-18 1984-09-18 Case for lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19498284A JPS6173358A (en) 1984-09-18 1984-09-18 Case for lsi

Publications (1)

Publication Number Publication Date
JPS6173358A true JPS6173358A (en) 1986-04-15

Family

ID=16333571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19498284A Pending JPS6173358A (en) 1984-09-18 1984-09-18 Case for lsi

Country Status (1)

Country Link
JP (1) JPS6173358A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0300434A2 (en) * 1987-07-21 1989-01-25 Sumitomo Electric Industries Limited Overcurrent protection circuit for semiconductor device
EP0632465A1 (en) * 1993-06-29 1995-01-04 Societe D'applications Generales D'electricite Et De Mecanique Sagem Low capacity read only memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0300434A2 (en) * 1987-07-21 1989-01-25 Sumitomo Electric Industries Limited Overcurrent protection circuit for semiconductor device
EP0632465A1 (en) * 1993-06-29 1995-01-04 Societe D'applications Generales D'electricite Et De Mecanique Sagem Low capacity read only memory
FR2708133A1 (en) * 1993-06-29 1995-01-27 Sagem Low capacity ROM.

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