JPS6162960A - Device scroll apparatus - Google Patents

Device scroll apparatus

Info

Publication number
JPS6162960A
JPS6162960A JP18460384A JP18460384A JPS6162960A JP S6162960 A JPS6162960 A JP S6162960A JP 18460384 A JP18460384 A JP 18460384A JP 18460384 A JP18460384 A JP 18460384A JP S6162960 A JPS6162960 A JP S6162960A
Authority
JP
Japan
Prior art keywords
selection
circuit
signal line
signal
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18460384A
Other languages
Japanese (ja)
Inventor
Keiji Minagawa
圭司 皆川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18460384A priority Critical patent/JPS6162960A/en
Publication of JPS6162960A publication Critical patent/JPS6162960A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To detect easily the erroneous insertion of plug-in by providing a selecting circuit which an errorneous insersion signal line, a gate circuit, and a selection impossiblility signal line. CONSTITUTION:A selecting circuit 25 is provided with an erroneous insetion signal line 19, a gate circuit 48, and a selection impossiblity signal; line 18. In case of erroneous insertion, the erroneous insertion signal line 19 is grounded through a mother board 35, and the selection impossbility signal line 28 is made active by the gate circiuit, and a control TAGBUS signal 13 and a selection holding signal 12 are gated by a receiver circuit 42. Thus, the selecting operation is impossible, and DISABLE is displayed on an ENABLE/DISABLE display device by the selection impossiblity signal line 18.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、デバイスクロスコール装置に係り、特に制御
装置と駆動装置のインターフェイス回路を搭載したプラ
グインの誤挿入時の誤動作に好適なデバイスクロスコー
ル装置に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a device cross call device, and in particular, a device cross call device suitable for malfunctions caused when a plug-in equipped with an interface circuit between a control device and a drive device is mistakenly inserted. Regarding equipment.

〔発明の背景〕[Background of the invention]

従来のデバイスクロスコール装置における制御装置(例
えば磁気ディスク制御装置)と駆動装置(例えば磁気デ
ィスク装置)のインターフェイス回路を搭載したプラグ
インの誤挿入時の不具合について、以下第1図から第5
図を用いて説明する。
Figures 1 to 5 below describe problems caused by incorrect insertion of a plug-in equipped with an interface circuit between a control device (for example, a magnetic disk control device) and a drive device (for example, a magnetic disk device) in conventional device cross-call devices.
This will be explained using figures.

第1図は、デバイスクロスコール装置のブロック図を示
している。この装置は、制御回路11及び制御回路21
の2系のパスより選択回路15及び選択回路25を経由
して、駆動回路51を制御を可能としている。シングル
コール構成時には制御回路21及び選択回路25は搭載
さねない(以下制御回路11のパスをA系と呼び、制御
回路21σ)パスをB系と呼ぶ) ENABLE / 
DISABLEスイッチ・表示器17及び27は、それ
ぞれの系の選択可/不可の操作を行なう。
FIG. 1 shows a block diagram of a device cross-call device. This device includes a control circuit 11 and a control circuit 21.
The drive circuit 51 can be controlled via the selection circuit 15 and the selection circuit 25 from two paths. In the case of a single call configuration, the control circuit 21 and the selection circuit 25 cannot be installed (hereinafter, the path of the control circuit 11 is called the A system, and the path of the control circuit 21σ is called the B system) ENABLE /
DISABLE switches/indicators 17 and 27 are used to enable/disable selection of each system.

駆動回路51の選択について第2図、第5図を用いて曲
、明する。第2図は選択回路15及び25を示す図であ
る。
The selection of the drive circuit 51 will be explained using FIGS. 2 and 5. FIG. 2 is a diagram showing selection circuits 15 and 25.

A系(制御装置11のパス)の選択の場合は、制御回路
11より選択保持信号線12とコントロー・ルTAG1
3AS信号線15で選択回路15に出力される・。
In the case of selecting the A system (path of the control device 11), the control circuit 11 connects the selection hold signal line 12 and the control TAG1.
is output to the selection circuit 15 via the 3AS signal line 15.

選択回路15ではこの信号をレシーバ回路42で受・け
、E#IBLE信号線16がアクティブ時のみTAGB
(JS信号を機番比較回路45に送る。機番比較回路4
5では駆動回路51からの機番信号線55とTAGB 
U S信号上の選択すべき機番との比較が行なわれ一致
がとれると機番一致信号線47をアクティブとする。こ
の時、選択回路25よりの選択時分割信号線24と選択
応答信号28がアクティブで邑1゜れば、ラッチ回路4
5がセットされ選択応答信号。
In the selection circuit 15, this signal is received by the receiver circuit 42, and TAGB is output only when the E#IBLE signal line 16 is active.
(Sends the JS signal to the machine number comparison circuit 45.
5, the machine number signal line 55 from the drive circuit 51 and TAGB
A comparison is made with the machine number to be selected on the US signal, and if a match is found, the machine number match signal line 47 is activated. At this time, if the selection time division signal line 24 and the selection response signal 28 from the selection circuit 25 are active and the latch circuit 4
5 is set as the selection response signal.

線14がアクティブとなって選択動作が完了する。Line 14 becomes active to complete the selection operation.

その後、制御回路11は選択応答信号線14がア。After that, the control circuit 11 outputs the selection response signal line 14 to A.

クチイブになった事を確認し、各種命令をコントロール
rAGBUs信号線15にのせて出力され、選択回路1
5でレシーバ回路42を経由してドライバ回路44に送
られる。ドライバ回路44は選択応答信号線14がアク
ティブであれば、駆動回路51にドライブi’AGBU
s信号線52を介して命令を出力し駆動する。
After confirming that the signal has been activated, various commands are output on the control rAGBUs signal line 15, and the selection circuit 1
5, the signal is sent to the driver circuit 44 via the receiver circuit 42. If the selection response signal line 14 is active, the driver circuit 44 causes the drive circuit 51 to drive i'AGBU.
A command is output via the s signal line 52 to drive.

B系からa)選択σ)場合もA系の場合と同様にして行
なわれろ。し、かしながら、クロスコール構成でA系か
ら選択状態にある場合、B系で制御回路21から選択命
令が出力されても、選択回路25において選択応答信号
線14がアクティブである為にラッチ回路45がセ・、
)されず選択が行なわれない。ところが第5図のように
A系とB系が同時に選択動作を行ない選択保持信号d(
A系)及びfCB系)が同時に立上った場合、ゲート遅
れの為に他系の選択動作を自系の選択応答信号e(/I
系)及びt(B系)で禁IFすることが出来ない。これ
を防ぐ為に選択回路25の時分割回路46に発振器信号
αを入力17、時分割信号す及びcf互い違いに出力す
る。この時分割信号すは選択回路15に送られラヴチ回
路45のセット信号をゲートする。又時分割信月CはA
系/B系切換器を通ってラッチ回路45のセ・ン)信月
をゲートする。従って、第5図で選択保持信’r4a及
びfが同時に立−にっても、時分割信号すが立上るまで
選択応答信号e及び9はセットさ・ 5 れない。時分割信号すが立上ると選択応答信号6がセ・
ノドされる。次に時分割信号Cが立上っても選択応答信
号eがセットされている為、選択応答信号9はセットさ
れない。選択保持信号dが落ち選択応答信号fがリセヴ
トされると、選択応答信号tはセットが可能となる。
For the case of a) selection σ) from system B, proceed in the same manner as for system A. However, when the A system is in the selection state in a cross-call configuration, even if a selection command is output from the control circuit 21 in the B system, the selection response signal line 14 is active in the selection circuit 25, so the latch is not activated. The circuit 45 is
) and no selection is made. However, as shown in FIG.
A system) and fCB system) rise at the same time, the selection response signal e (/I
system) and t (B system) cannot be inhibited. In order to prevent this, the oscillator signal α is input 17 to the time division circuit 46 of the selection circuit 25, and the time division signals S and CF are alternately outputted. This time-division signal is sent to the selection circuit 15 and gates the set signal of the Lavchi circuit 45. Also, time-sharing Shingetsu C is A
The signal of the latch circuit 45 is gated through the system/B system switch. Therefore, even if the selection hold signals 'r4a and f rise simultaneously in FIG. 5, the selection response signals e and 9 are not set until the time division signal rises. When the time division signal 6 rises, the selection response signal 6
Get throated. Next, even when the time division signal C rises, the selection response signal 9 is not set because the selection response signal e is set. When the selection holding signal d falls and the selection response signal f is reset, the selection response signal t can be set.

1〜かしながら、選択回路15と選択回路25とが誤ま
って挿入されると、A系/B系切換器の設定が異なる為
、A系では発振器信号線S4が入力されておらず時分割
信号りは常時アクティブ状態となり、又B系においても
時分割暗号線28が入力されない為、プルアップされて
常時アクティブ状態となり、同一駆動回路を二つの系よ
り同時に選択する為データ破壊やシステムダウンのよう
な重要障害に結びつき、自己診断による誤挿入の指摘も
回船であるという欠点があった。
However, if the selection circuit 15 and the selection circuit 25 are inserted by mistake, the settings of the A system/B system switch will be different, and the oscillator signal line S4 will not be input to the A system. The divided signal is always active, and since the time division code line 28 is not input in system B, it is pulled up and always active, and the same drive circuit is selected from two systems at the same time, resulting in data destruction or system down. This leads to serious failures such as the following, and the problem is that self-diagnosis is not enough to point out incorrect insertion.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、前記従来技術の問題点を除去すること
であり、プラグインの誤挿入に際してもその検知を行な
うことができるデバイスクロスコール装置を梯供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the prior art described above, and to provide a device cross-call device that can detect erroneous insertion of a plug-in.

〔発明の概要〕[Summary of the invention]

原価低減の為、同一基板を使用し、多少の変更を行ない
他用途に使用するということが多用されて来ているが、
そのような基板同志が誤挿入された場合には、簡易なテ
ストプログラムによる検出が不明となる。この為、誤挿
入により回路誤動作により重大な障害に結びつく危険性
をもっている。
In order to reduce costs, it has become common to use the same board, make some changes, and use it for other purposes.
If such boards are inserted incorrectly, detection by a simple test program will become unclear. Therefore, there is a risk that incorrect insertion may lead to circuit malfunction, leading to serious trouble.

しかしながら、プラッタとマザーボード両者を使って対
策することにより容易に解決することが出来る。
However, this problem can be easily solved by using both the platter and the motherboard.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第4図を用いて説明する。 Hereinafter, one embodiment of the present invention will be described using FIG. 4.

本実施例の特徴は、選択回路25に誤挿入信号線19、
ゲート回路4B及び選択不可信号線18を設けたことで
ある。
The feature of this embodiment is that the selection circuit 25 includes an erroneous insertion signal line 19;
This is because the gate circuit 4B and the non-selectable signal line 18 are provided.

すなわち、第4図に示すように誤挿入が行なわれた場合
、B系からは常時選択可能となるが、A系においては、
誤挿入信号線19がマザーボー。
In other words, if an incorrect insertion is made as shown in Figure 4, selection is always possible from system B, but in system A,
The incorrectly inserted signal line 19 is the motherboard.

ド55を経由して接地される為、ゲ・−ト回路48で選
択不可信号線18をアクティブにし、レシーバ回路42
でコントロールTAGBUS信号15及び選択保持信号
12をゲートする。これ圧よりA系からの選択動作を不
可とし、選択不可信号線18によってENABLE /
 Dis、4BLE表示器をI)ISABLF。
Since it is grounded via the gate circuit 48, the unselectable signal line 18 is activated and the receiver circuit 42 is grounded via the gate circuit 48.
The control TAGBUS signal 15 and the selection hold signal 12 are gated. This pressure disables the selection operation from the A system, and the selection disable signal line 18 causes the ENABLE/
Dis, 4BLE display I) ISABLF.

表示させる。Display.

従って、本実施例によれば、プラグインの誤挿入による
障害を未然に防止すると同時に誤挿入があった時の検出
方法を容易にする効果がある。
Therefore, according to this embodiment, it is possible to prevent failures due to erroneous plug-in insertion, and at the same time, to facilitate the detection method when erroneous insertion occurs.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、類似プラグインの誤挿入の検知方法が
容易となった。もし仮りに、表示が見過されても誤動作
を未然に防ぐ効果がある。
According to the present invention, a method for detecting erroneous insertion of a similar plug-in has become easier. Even if the display is overlooked, it is effective in preventing malfunctions.

又、本発明によればマザーボードの布線追加は必要とし
ても、片系のプラグインにのみ回路追加を行なうだけで
良く経済的にも好適である。
Furthermore, according to the present invention, even if additional wiring is required on the motherboard, it is only necessary to add circuitry to one plug-in system, which is economically advantageous.

・ 7 ・・ 7 ・

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、ドライブクロスコール装置のブロック図。第
2図は、従来の選択回路のブロック図、第5図は、第2
図で説明に供される波形図。 第4図は、本発明によるプラグイン誤挿入の検知・誤動
作防止を行なうドライブスクロール装置の選択回路のブ
ロック図。
FIG. 1 is a block diagram of a drive cross call device. FIG. 2 is a block diagram of a conventional selection circuit, and FIG. 5 is a block diagram of a conventional selection circuit.
FIG. 2 is a waveform diagram provided for explanation. FIG. 4 is a block diagram of a selection circuit of a drive scroll device that detects erroneous plug-in insertion and prevents malfunction according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 2つの制御装置より異なったルートを介して、複数の駆
動装置の制御を行なうと共に、第1の選択回路に挿入さ
れる第1のプラグインと、第2の選択回路に挿入される
第2のプラグインとを備えるデバイスクロスコール装置
において、第2のプラグインが少なくとも2つの端子を
短絡する信号線を持つと共に、第1の選択回路が該第2
のプラグインが挿入された場合に該第2のプラングイン
のみが動作する様に構成されていることを特徴とするデ
バイススクロール装置。
A plurality of drive devices are controlled by two control devices via different routes, and a first plug-in inserted into a first selection circuit and a second plug-in inserted into a second selection circuit are controlled. In the device cross-call device comprising a plug-in, the second plug-in has a signal line that shorts at least two terminals, and the first selection circuit has a signal line that shorts at least two terminals, and the first selection circuit
A device scrolling device characterized in that the device scrolling device is configured such that only the second plug-in operates when the second plug-in is inserted.
JP18460384A 1984-09-05 1984-09-05 Device scroll apparatus Pending JPS6162960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18460384A JPS6162960A (en) 1984-09-05 1984-09-05 Device scroll apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18460384A JPS6162960A (en) 1984-09-05 1984-09-05 Device scroll apparatus

Publications (1)

Publication Number Publication Date
JPS6162960A true JPS6162960A (en) 1986-03-31

Family

ID=16156098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18460384A Pending JPS6162960A (en) 1984-09-05 1984-09-05 Device scroll apparatus

Country Status (1)

Country Link
JP (1) JPS6162960A (en)

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