JPS6159869A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6159869A
JPS6159869A JP18063084A JP18063084A JPS6159869A JP S6159869 A JPS6159869 A JP S6159869A JP 18063084 A JP18063084 A JP 18063084A JP 18063084 A JP18063084 A JP 18063084A JP S6159869 A JPS6159869 A JP S6159869A
Authority
JP
Japan
Prior art keywords
polysilicon layer
mask
polysilicon
base
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18063084A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
広志 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18063084A priority Critical patent/JPS6159869A/en
Publication of JPS6159869A publication Critical patent/JPS6159869A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/732Vertical transistors
    • H01L29/7325Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To stabilize the steps by growing the first polysilicon layer after recessing an oxide film of a silicon substrate, selectively removing the polysilicon layer, and growing the second polysilicon layer on the single crystal silicon and polysilicon layer of the substrate. CONSTITUTION:With a mask 31 an oxide film 30 is selectively etched to form in a structure that the surface of the film 30 is recessed on the surface of a silicon substrate 11, and a polysilicon layer 32 is grown on the entire upper surface of the substrate 11. When the upper surface is then etched, the layer 32 is selectively retained on the same plane as the mask 31 in the stage of exposing the mask 31. Subsequently, the remaining mask 31 is removed, and, when then epitaxially grown, a polysilicon layer 34 is grown on the layer 32, and a single crystal silicon 33 is grown on the substrate 11. Then, a base and an emitter are formed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の製法に関するものであシ、さらに
詳しく述べるならばポリシリコンを用いて内部ベースの
側面に外部ベースコンタクトをとる 。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to making an external base contact on the side surface of an internal base using polysilicon.

パイ−−ラトランジスタを形成する工程を含む半導体装
置の製造方法に関するものである。
The present invention relates to a method of manufacturing a semiconductor device including a step of forming a pieral transistor.

(従来の技術) パイ?−ラトランジスタのプレーナ構造ではベース面積
が非常に大きくなるために、ベース・コレクタ間容量お
よびベース抵抗が大きくなるという問題がある。このよ
うな問題を解消するために、米国特許第3,600,6
51号明細書によると、第7図に示す如きバイポーラト
ランジスタが提案されている。すなわち、N型シリコン
基板10上にSiO□膜12全12的に形成し、SiO
□膜12全12部上には単結晶シリコン層14をエピタ
キシャル成長させ、5IO2膜12上には一すシリコン
IC16を成長させ、これらのシリコン層14.16を
L)型にドーピングすることにより、P型の単結晶シリ
コン層14は内部ベース領域として、一方P型の、j?
 IJシリコン層16はベース領域側面に導通をとる外
部ベースコンタクトとして用いられる。
(Conventional technology) Pie? - Since the planar structure of the transistor has a very large base area, there is a problem that the base-collector capacitance and base resistance become large. In order to solve this problem, U.S. Patent No. 3,600,6
According to the specification of No. 51, a bipolar transistor as shown in FIG. 7 is proposed. That is, all 12 SiO□ films 12 are formed on the N-type silicon substrate 10, and the SiO
□A single-crystal silicon layer 14 is epitaxially grown on all 12 parts of the film 12, a silicon IC 16 is grown on the 5IO2 film 12, and these silicon layers 14 and 16 are doped with L) type. A monocrystalline silicon layer 14 of type P, on the other hand, serves as an internal base region, j?
The IJ silicon layer 16 is used as an external base contact to provide electrical conduction to the side surface of the base region.

°上記シリコン層14.16上に選択的に形成された5
IO2膜18の単結晶シリコン層(ベース領域)14上
の開孔部にはN型の不純物をドーピングして、エミッタ
領域20とし、一方−リシリコン層16上の開孔部22
はベースコンタクト窓として使用する。このようなバイ
ポーラトランジスタ構造によると、ベース・コレクタ間
容量が小さくなるためにスイッチングスピードの増大が
期待される。しかしながら、IC製造工工程採用される
LOCO8によ多形成されるフィールド絶縁膜上に外部
ベースとなるポリシリコン層を形成することは困難であ
り、また内部ベースと外部ベースの間に段差が形成され
るため段差部で導通不良が生じるおそれがある。
5 selectively formed on the silicon layer 14.16
The opening on the single crystal silicon layer (base region) 14 of the IO2 film 18 is doped with N-type impurities to form the emitter region 20, while the opening 22 on the silicon layer 16
is used as a base contact window. According to such a bipolar transistor structure, an increase in switching speed is expected because the base-collector capacitance is reduced. However, it is difficult to form a polysilicon layer that serves as an external base on the field insulating film that is formed in the LOCO8 process used in the IC manufacturing process, and a step is formed between the internal base and the external base. Therefore, there is a risk that poor conduction may occur at the stepped portion.

(発明が解決しようとする問題点) 上記米国特許の方法においてStO□@12上へノホリ
シリコンの成長は、単結晶シリコン14のエピタキシャ
ル成長が実現される条件下では困難であるために、5I
O2膜上にポリシリコン成長のだめの核が存在していな
いと、ポリシリコン層16の成長は期待できない。第1
図に示す如く、一般のIC製造に多用されるLOCO8
により、窒化膜31をマスクとしてシリコン基板上11
に形成されるフィールド酸化膜30上にはポリシリコン
成長の核となるものが存在しないために内部ベース形成
用エピタキシャル成長売件下で、外部ベース用ポリシリ
コンを成長させることは困難でおる。
(Problems to be Solved by the Invention) In the method of the above-mentioned US patent, it is difficult to grow silicon on StO□@12 under the conditions in which epitaxial growth of single crystal silicon 14 is achieved.
If there are no nuclei for polysilicon growth on the O2 film, growth of the polysilicon layer 16 cannot be expected. 1st
As shown in the figure, LOCO8, which is often used in general IC manufacturing.
11 on the silicon substrate using the nitride film 31 as a mask.
Since there is no nucleus for polysilicon growth on the field oxide film 30 formed in the field oxide film 30, it is difficult to grow polysilicon for the external base under epitaxial growth conditions for forming the internal base.

(問題点を解決するための手段および作用)本発明は、
ポリシリコンを用いて内部ベースの側面に外部ベースコ
ンタクトをとるパイ?−ラトランジスタ形成する工程を
含む半導体装はの製造方法において、シリコン基板の表
面に耐酸化性マスクを用いて選択的に形成した酸化膜を
基板表面に対して窪捷せた後に該シリコン基板上に第1
のポリシリコン層を成長させ、次にこの第1のポリシリ
コン層を選択的に除去して前記マスクを表出後このマス
ク除去によシ表出された基板の単結晶シリコンおよび前
記第1C)ポリシリコン層上に第2のポリシリコン層を
成長させることによシ、前記単結晶シリコン上には内部
ベース形成用単結晶シリコンおよび前記第1のポリシリ
コン上には外部ベース形成用/ IJシリコンをそれぞ
れ形成することを特徴とし、この特徴によって選択酸化
膜上に外部ベース用ポリシリコン成長の核となる第1の
ポリシリコン層を成長させ、以って内部ベース用単結晶
シリコンと外部ベース用多結晶シリコンを通常のエピタ
キシャル成長条件により同時に形成できるようにしたも
のである。
(Means and effects for solving the problems) The present invention has the following features:
A pie that uses polysilicon to make external base contacts to the sides of the internal base? - In a method of manufacturing a semiconductor device including a step of forming a transistor, an oxide film selectively formed on the surface of a silicon substrate using an oxidation-resistant mask is recessed on the surface of the silicon substrate, and then the oxide film is formed on the silicon substrate. 1st to
After growing a polysilicon layer of the first polysilicon layer and then selectively removing this first polysilicon layer to expose the mask, the single crystal silicon of the substrate exposed by this mask removal and the first polysilicon layer (1C) By growing a second polysilicon layer on the polysilicon layer, single crystal silicon for forming an internal base is formed on the single crystal silicon, and /IJ silicon for forming an external base is formed on the first polysilicon. This feature allows the first polysilicon layer to be grown on the selective oxide film to serve as the nucleus for the growth of polysilicon for the external base, thereby forming single crystal silicon for the internal base and single crystal silicon for the external base. This allows polycrystalline silicon to be formed simultaneously under normal epitaxial growth conditions.

(実施例) 以下、本発明の実施例を第1図−第6図によシ説明する
(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 6.

第1図において、30は通常のLOCO8またはROX
によ多形成された5IO2などの、素子分離用酸化膜、
31は513N4などの選択酸化用マスクである。第2
図以降の図面を参照として、酸化膜30上に外部ベース
形成用ポリシリコンを形成するとともにマスク31によ
フ被覆されたn型コレクタ領域上に内部ベースおよびエ
ミッタを形成するプロセスを説明する。尚、n型コレク
タ領域は通常良く知られているようにp型基板10上に
高濃度n型埋没層及びコレクタリーチスルー領域37を
含むエピタキシャルT6Jllで形成されている。
In Figure 1, 30 is a normal LOCO8 or ROX
An oxide film for element isolation, such as 5IO2,
31 is a mask for selective oxidation such as 513N4. Second
The process of forming polysilicon for forming an external base on the oxide film 30 and forming an internal base and emitter on the n-type collector region covered by the mask 31 will be described with reference to the subsequent drawings. Incidentally, the n-type collector region is formed of an epitaxial T6Jll including a high concentration n-type buried layer and a collector reach-through region 37 on the p-type substrate 10, as is generally well known.

第2図のプロセスにおいては、マスク31を用いて酸化
膜30をバッファー弗酸等を用いた湿式法によシ選択的
にエツチングして酸化膜30の表面がシリコン基板11
の表面に対して窪んだ構造が得られる。この窪みの深さ
は特に制限的ではないが0.3ミクロン以上が好ましい
In the process shown in FIG. 2, the oxide film 30 is selectively etched using a mask 31 by a wet method using buffered hydrofluoric acid, so that the surface of the oxide film 30 is etched onto the silicon substrate 1.
A concave structure is obtained with respect to the surface. Although the depth of this depression is not particularly limited, it is preferably 0.3 microns or more.

続いて第3図のプロセスにおいて、CvDによって第1
のポリシリコン層32をシリコン基板11の上面全体に
成長させる。なお、CvD成長の条件はシラン(5in
4)を600〜700℃、1〜50pa(z?スカル)
の減圧条件で分解させるCVDとすると、成長性にすぐ
れたポリシリコンの成長を行なうことができる。
Next, in the process shown in Figure 3, the first
A polysilicon layer 32 is grown over the entire upper surface of the silicon substrate 11. The conditions for CvD growth are silane (5 in.
4) at 600-700℃, 1-50pa (z?skull)
If CVD is used to decompose under reduced pressure conditions, polysilicon with excellent growth properties can be grown.

次に、第4図のプロセスにおいて、上面の工。Next, in the process shown in Figure 4, the top surface is machined.

チング、ポリシングまたはラッピングを行なうと、マス
ク31が表出された段階で第1のポリシリコン層32の
除去が停止して、マスク31と同一平面で第1のポリシ
リコン層32が選択的に残される。但し、エツチングを
行なう場合はエツチング時間を制御してポリシリコン層
32を選択的に除去する必要があシ、一方?リジング等
の場合は硬いS l 3N4からなるマスク31がポリ
シング等のストッパーになる。続いて、第4図のプロセ
ス完了時に残っているマスク31を除去すると、外部ベ
ース形成領域および内部ベース・エミッタ形成領域にそ
れぞれポリシリコン(32)およびシリコン基板11の
単結晶シリコンが存在する構造が得られるので、外部ベ
ース形成領域には、d IJシリコンの核が生成されて
いることになる。
When etching, polishing, or lapping is performed, removal of the first polysilicon layer 32 is stopped when the mask 31 is exposed, and the first polysilicon layer 32 is selectively left in the same plane as the mask 31. It will be done. However, when etching is performed, it is necessary to control the etching time to selectively remove the polysilicon layer 32. On the other hand? In the case of ridging, etc., the mask 31 made of hard S 1 3N4 serves as a stopper for polishing, etc. Subsequently, when the remaining mask 31 is removed when the process shown in FIG. This means that d IJ silicon nuclei are generated in the external base formation region.

続いて、第5図のプロセスにおいて通常のエピタキシャ
ル成長条件でシリコンの成長を行なうと、第1のポリシ
リコン層32の上には第2のポリシリコン層34が、シ
リコン基板11上には単結晶シリコン33がそれぞれ成
長する。この成長プロセスの前段プロセスでポリシリコ
ンの核が生成されでいるために、結晶性のよい単結晶シ
リコン33を得るための通常のエピタキシャル成長条件
下でも、ポリシリコンが34で示した如く成長する。
Subsequently, when silicon is grown under normal epitaxial growth conditions in the process shown in FIG. 33 each grow. Since polysilicon nuclei have not yet been generated in the preceding process of this growth process, polysilicon grows as shown at 34 even under normal epitaxial growth conditions for obtaining single crystal silicon 33 with good crystallinity.

なお、この成長条件は、例えば1000〜1100℃、
1〜100 Paの条件であってよい。
Note that this growth condition is, for example, 1000 to 1100°C,
The conditions may be 1 to 100 Pa.

続いて、第7図と類似の構造を得るために、第6図のプ
ロセスにおいて通常の手法によυベースおよびエミッタ
を形成する。即ち、ベース領域及びコレクタコンタクト
領域等活性領域として用いられないポリシリコンを選択
酸化等を利用し酸化膜41を形成した後、適当なマスク
を用いてベース領域40にはポロン々どのp型不純物を
イオン注入する。このとき活性領域表面には熱酸化膜4
2が形成されている。尚、必要とあれば、ベース領域形
成後にベースコンタクト部分のみを適当なマスクを用い
てp型不純物を高濃度に注入しておくことも可能である
。その後、この熱酸化膜にエミツタ窓39、ベースコン
タクト窓38、コレクタコンタクト窓43を開口した後
、適当なマスクを用いて、エミツタ窓、コレクタコンタ
クト窓内に1s等の罐不純物をイオン注入等で形成し、
エミッタ領域及びコレクタコンタクト補償拡散領域を形
成する。
Subsequently, in order to obtain a structure similar to that shown in FIG. 7, the υ base and emitter are formed by a conventional method in the process shown in FIG. That is, after forming an oxide film 41 using selective oxidation or the like on polysilicon that is not used as an active region such as a base region and a collector contact region, p-type impurities such as boron are added to the base region 40 using an appropriate mask. Implant ions. At this time, a thermal oxide film 4 is formed on the surface of the active region.
2 is formed. If necessary, it is also possible to implant p-type impurities at a high concentration into only the base contact portion using an appropriate mask after forming the base region. After that, after opening an emitter window 39, a base contact window 38, and a collector contact window 43 in this thermal oxide film, using an appropriate mask, can impurities such as 1S are implanted into the emitter window and collector contact window by ion implantation, etc. form,
Form an emitter region and a collector contact compensation diffusion region.

(効果) 本発明によると、LoCO8またはROXによる選択酸
化膜上に外部ベースコンタクト用ポリシリコンが形成さ
れるために、LOCO8またはROX工程を伴う半導体
装fffi造において、内部ベースの側面に外部ベース
コンタクトをとるバイポーラトランジスタを製造するこ
とができる。
(Effects) According to the present invention, since polysilicon for an external base contact is formed on a selective oxide film formed by LoCO8 or ROX, an external base contact is formed on the side surface of an internal base in a semiconductor device fffi structure that involves a LOCO8 or ROX process. It is possible to manufacture a bipolar transistor that takes

さらに、上記半導体装置において外部ベースコンタクト
用ポリシリコン形成において減圧CVDによシポリシリ
コン成長の核を形成させた後に選択エピタキシャル成長
を行なうと、選択エピタキシャル成長が安定して行なわ
れる。
Further, in the above semiconductor device, when selective epitaxial growth is performed after forming polysilicon growth nuclei by low pressure CVD in forming polysilicon for an external base contact, selective epitaxial growth can be performed stably.

さらに、また選択エピタキシャル成長においてポリシリ
コン層と単結晶シリコン層が平坦化されるので、外部ベ
ースと内部ベースの接続部が酸化膜の段差に沿わないた
め、断線等の危険も少なくなる。
Furthermore, since the polysilicon layer and the single-crystal silicon layer are planarized during selective epitaxial growth, the connection between the external base and the internal base does not follow the step of the oxide film, which reduces the risk of wire breakage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図−第6図は本発明に係る方法の一実施例を説明す
る工程図、 第7図は従来のバイポーラトランジスタの断面図である
。 11・・・シリコン基板、30・・・酸化膜、31・・
・マスク、32・・・第1のポリシリコン層、33・・
・単結晶シリコン、34・・・第2の都すシリコン層。 特許量、願人 μ士通株式会社 特許出日代理人
1 to 6 are process diagrams illustrating an embodiment of the method according to the present invention, and FIG. 7 is a sectional view of a conventional bipolar transistor. 11... Silicon substrate, 30... Oxide film, 31...
-Mask, 32...first polysilicon layer, 33...
- Single crystal silicon, 34... second capital silicon layer. Patent volume, applicant Mujitsu Co., Ltd. Patent Depth Agent

Claims (1)

【特許請求の範囲】 1、ポリシリコンを用いて内部ベースの側面に外部ベー
スコンタクトをとるバイポーラトランジスタを形成する
工程を含む半導体装置の製造方法において、 シリコン基板の表面に耐酸化性マスクを用いて選択的に
形成した酸化膜を基板表面に対して窪ませた後に該シリ
コン基板上に第1のポリシリコン層を成長させ、次にこ
の第1のポリシリコン層を選択的に除去して前記マスク
を表出後このマスク除去により表出された基板の単結晶
シリコンおよび前記第1のポリシリコン層上に第2のポ
リシリコン層を成長させることにより、前記単結晶シリ
コン上には内部ベース形成用単結晶シリコンをおよび前
記第1のポリシリコン上には外部ベース形成用ポリシリ
コンをそれぞれ形成することを特徴とする半導体装置の
製造方法。
[Claims] 1. A method for manufacturing a semiconductor device including the step of forming a bipolar transistor with an external base contact on the side surface of an internal base using polysilicon, the method comprising: using an oxidation-resistant mask on the surface of a silicon substrate; After recessing the selectively formed oxide film relative to the substrate surface, a first polysilicon layer is grown on the silicon substrate, and then this first polysilicon layer is selectively removed to form the mask. After exposing the mask, a second polysilicon layer is grown on the single crystal silicon of the substrate exposed by removing the mask and the first polysilicon layer, so that a second polysilicon layer is grown on the single crystal silicon for forming an internal base. A method of manufacturing a semiconductor device, comprising forming single crystal silicon and polysilicon for forming an external base on the first polysilicon.
JP18063084A 1984-08-31 1984-08-31 Manufacture of semiconductor device Pending JPS6159869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18063084A JPS6159869A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18063084A JPS6159869A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6159869A true JPS6159869A (en) 1986-03-27

Family

ID=16086555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18063084A Pending JPS6159869A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6159869A (en)

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