JPS615523A - Method of dry etching - Google Patents

Abstract

PURPOSE:To machine a high melting point metal in a directional property without damaging a GaAs substrate by using NF3 gas for reactive gas in the step of ultrafinely machining the metal formed on a compound semiconductor by a reactive ion etching method. CONSTITUTION:NF3 gas is used for reactive gas in the step of ultrafinely machining a high melting point metal formed on a compound semiconductor by a reactive ion etching method. For example, tungsten silicide 2 is coated by sputtering on a crystal formed with an N type active layer 10 on a semi-insulating GaAs substrate 1. A gate pattern 20 of the desired size is formed of photoresist, a tungsten silicide 3 is machined by reactive ion etching method using mixture gas of NF3 gas and N2 with it as a mask. Thus, since the metal can be machined with good controllability without damaging the GaAs, an integrated circuit using GaAs semiconductor can be performed in high performance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a dry etching method for refractory metals used in semiconductor integrated circuits, and particularly to a dry etching method suitable for GaAs semiconductors.

[Background of the invention]

For dry etching of tungsten silicide metal, which is a high melting point metal used in conventional GaAs-ICs, a reactive ion etching method using CF and 02 gas has been used. An example of this is Yokoya
ma et al: IEHE Transacti
ons onElectron Devices p1
541 vol, HD-29, &IOOct.

Seen in 1982 etc. The manufacturing procedure for this device is shown in FIG. First, a tungsten silicide metal 2 having a high melting point is deposited on the n-type active layer lo of the GaAs substrate 1 (see figure (a)). Next, a gate electrode 3 is formed using photoresist as a mask ( Figure (b)).

In the conventional dry etching method, when forming the gate electrode 3, the selectivity between the GaAs substrate and tungsten silicide is low, so a part of the GaAs layer 4 is etched and dry etching damage is induced in the crystal.
It was thought that the device was the main cause of performance degradation. Therefore, in order to prevent GaAs from being removed by dry etching, it was necessary to optimize the two etching time conditions, but the C1''4 gas system had the drawback of poor process margin.

(Objective of the Invention) The object of the present invention is to microfabricate a high melting point metal used in a GaAs semiconductor integrated circuit by reactive ion etching.
It is an object of the present invention to provide a dry etching method that can process a high melting point metal directionally without damaging a GaAs substrate.

[Summary of the invention]

The fact that GaAs can be etched by dry etching with CF 4 gas suggests that sputtering was caused by ion bombardment rather than chemically. Therefore, as a result of investigating the ion impact energy of several types of fluorine-based gases, it was found that CF4>NF3. Therefore, the degree to which GaAs is etched by both gases was compared. Figure 2 shows CF4 gas and NF, with constant RF power and gas flow rate.
Figure 3 shows gas pressure dependence of aAs etching rate. NF
It can be seen that z gas causes almost no etching compared to CF4 gas. This result is consistent with the relationship of ion bombardment energy. In addition to GaAs, the etching rates of photoresist and tungsten silicide (WSi) were investigated. These are shown in Table 1 as etching rate ratios for each gas. As you can see from the same table, WS
It can be seen that in the case of processing i, NF3 gas is superior even when looking at these etching speed ratios. In Figure 3 and Table 1, the comparison was made using pure CF4 gas, but the etching rate CF of Gaps,
It was found that the difference was larger when 02 was mixed with. NF, ni0
Mixing N2 with NF increases the etching speed of the resist, which is not desirable, but mixing N2 with NF has an improving effect.

Figure 3 is NF.

The relationship between the etching rate of tungsten silicide and GaAs when Nz is mixed in the gas is shown. The tungsten silicide etching rate decreases as N2 increases, and the addition of N2 is effective in improving the controllability of the tungsten silicide etching rate. Furthermore, the GaAs etching rate j does not depend on N2 and remains almost zero. FIG. 4 shows the cross-sectional shape of tungsten silicide due to the N2 mixing effect. N
In the case of F, gas only, the tungsten silicide 3 processed on the GaAs substrate 1 is slightly side etched 5.
In the case of NF3+N2 gas, the tungsten silicide 3 processed on the GaAs substrate 1 is etched almost directionally (Fig. 4(a)).
b)). This is considered to be because the N2 mixture reduces the number of neutral particles and has the effect of preventing side etching.

Even when He was mixed into the mixed gas of NF2 gas and N2=S, the relationship shown in FIG. 3 was maintained, and uniformity within the wafer surface was improved by mixing He.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Tungsten silicide 2 was deposited by sputtering on a crystal on which an n-type active layer 1o was formed on a semi-insulating GaAs substrate 1 (thickness: 400 nm).

A gate pattern 2o of desired dimensions was formed by photoresist (FIG. 6(a)). Using this as a mask, the tungsten silicide 3 was processed by the dry etching method of the present invention. The etching conditions were as follows.

Frequency method: 13.56 MHz, parallel plate type RF power density: 0.10 W/, d Gas type: N, F s
10Nz Mixing ratio: 0.2 (NFi /NFi +N2)
Total flow rate: 20 mA/win Gas pressure: 5 Pa The processed cross section was almost vertical, and the amount of side etching was less than 0.1 μm (FIG. 2(b)).

As shown in Figure 3, under these etching conditions, GaAs
The etching and damage of GaAs, which had been a problem in the past, could be completely solved. After processing the gate, St ions, which will become the highly doped n-type layer 30, are implanted from the surface (FIG. 3(C)). Through this process, the area around the tungsten silicide gate 3 becomes the highly doped n-type layer 30. Self-lined, effective in reducing series resistance.

Next, after heat treatment at 800℃ for 10 minutes, sauce 4
1. A GaAs FET element was made by attaching it to the drain 42 electrode (FIG. 4(d)). GaA produced by the method of the present invention
S-FETs, diodes, resistors, and capacitors are free from defects such as scratches and scratches on the GaAs surface due to dry etching, which not only improves the performance of FETs but also improves the ability to form integrated circuits. I would like to add that this has enabled us to control and manufacture the resistors, capacitances, etc. in accordance with the design values, which has led to a significant improvement in device yield.

In the above embodiments, a photoresist is used as a processing mask for tungsten silicide, but a material with a slow etching rate such as SiO□ or PSG may also be used for this mask machine.

Furthermore, although tungsten silicide has been described as an example of a high melting point metal, the present invention is not limited to it; for example,
W alone, W-Ti alloy, W-Ti/St gold alloy Mo,
It can also be applied to materials such as Mo-8i alloy.

Further, although the method of processing high melting point metal on Gaps semiconductor has been described as an example, the dry etching method according to the present invention can be applied to other compound semiconductors (for example, InP).

It can also be applied to materials formed on materials such as GaA Q As, and is not limited to GaAs.

〔Effect of the invention〕

According to the present invention, it is possible to process a high melting point metal with good controllability without cutting the GaAs substrate crystal and without damaging GaA+, so it is possible to realize a high-performance integrated circuit using a GaAs semiconductor. This has the effect of improving device yield.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of conventional integrated circuit gate processing, Figure 2 is a diagram showing the dependence of GaAs etching rate on gas pressure, Figure 3 is a diagram showing the dependence of etching rate on N2 mixture, and Figure 4 is a diagram showing the dependence of etching rate on N2 mixture.
The figure is a cross-sectional view of gate processing using N2 mixture, and FIG. 5 is a cross-sectional view of the order of manufacturing steps of a GaAs-FET according to an embodiment of the present invention. 1... Semiconductor GaAs substrate, 2... High melting point metal,
3... Gate pattern, 4... Damaged portion of GaAs substrate, 5... Side etched portion of gate, 10... N-type GaAa layer.

Claims (1)

[Claims] 1. A dry etching method characterized in that NF_3 gas is used as a reactive gas in the step of finely processing a high melting point metal formed on a compound semiconductor by a reactive ion etching method. 2. The dry etching method according to claim 1, characterized in that N_2 gas is mixed with the above gas. 3. A dry etching method according to claim 2, characterized in that He is further added to the mixed gas. 4. The dry etching method according to claims 1 to 3, characterized in that GaAs is used as the compound semiconductor.