JPS615492A - Memory device - Google Patents

Abstract

PURPOSE:To attain simultaneously the reduction in power consumption of a memory device and its speed-up by activating memory cells of bistable circuit only when active and passive loads for comprising said circuits together with two sets of switching elements are not selected or selected. CONSTITUTION:Memory cells of bistable circuit are constituted of two sets of npn bipolar transistors Q1 and Q2 for forming a cross-linking switching element and a load, which is formed by pnp bipolar transistors Q3 and Q4 connected to a word line W2 and resistances R1 and R2 connected to a word line W1. The resistances R1 and R2 and the transistors Q3 and Q4 serve as a load at the time of selection of the memory cell and at the time of non-selection of said cell, respectively. Accordingly an action speed at selection is sped up, and a holding current at nonselection is reduced; therefore the reaction in power consumption of the memory device and its speed-up can be obtained simultaneously.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to storage device technology and also to semiconductor devices. For example, it can be used to reduce power consumption and speed up bipolar static RAM. It is related to effective technology.

[Background technology]

For example, static RAM is one of the storage devices that is widely used. This stack R
Most AMs use a bistable circuit configured with two sets of switching elements and a load as a memory cell.

Among static R and AM types, bipolar types in particular are generally high-speed, and are therefore often used together with ECL and the like in applications that require high-speed performance.

By the way, taking the bipolar type static RAM as an example, this type of RAM is classified according to the type of load used in its memory cell. There are two main classifications.

One of them is to use a passive element such as a resistor as a load. The other type is to actively operate an active element such as a transistor as a load. An example of the latter is 1, for example, VLSI Handbook 340, 3 published by Science Forum Co., Ltd. on November 28, 1983.
The pnp load storage cell described on page 41 is typical.

FIG. 1 shows an example of a memory cell used in a bipolar static RAM. The memory cell shown in the figure forms a type of bistable circuit, and is composed of two sets of switching elements and a passive load. NPN bipolar transistors Ql and Q2 are used as switching elements. Furthermore, resistors R1 and R2 are used as passive loads.

The collectors of the transistors Q], , Q2 are connected to the word line W via resistors R1 and R2, respectively.

Further, transistors Ql and Q2 each have two emitter electrodes. Each one of the emitter electrodes is commonly connected to a word return line C.

The other emitter electrodes are connected to the bit lines Bl and B, respectively.
Connected to 2. Reading or writing memory data is
This is done via the bit lines B1 and B2.

The passive load type memory cell shown in FIG. 1 has the advantage that it can operate at high speed because the transistors Ql and Q2 operate in a non-saturated (or low-saturated) state. However, for this reason, a relatively large current must continue to flow through one of the resistors R1 and R2 even when not selected. In other words, there is a drawback that a large amount of holding current is required during non-selection, which increases the power consumption of the entire storage device.

FIG. 2 shows another example of a memory cell used in a bipolar static RAM. The memory cell shown in the figure is also a type of 2
Forms a stable circuit. This memory cell is composed of two sets of switching elements and an active load. In this memory cell,
The switching element is an npn bipolar transistor Ql.

Q2 is used, but the active element pn is used as a load.
p-type bipolar transistor Q3. Q4 is used.

Each transistor Ql, Q2 as a switching element
The collectors of the transistors are respectively connected to the word line W via pnp bipolar transistors Q3 and Q4, which are active loads. Further, transistors Ql and Q2 as switching elements each have two emitter electrodes. The emitter electrodes on each side are connected in common to the word return line C.
connected. The other emitter electrodes are connected to bit lines B1 and B2, respectively. Reading or writing of stored data is performed via the bit lines BL, B2.

In the active load type memory cell shown in the same figure, contrary to the case shown in FIG.
3. The conduction state of Q4 also changes.

In other words, the load impedance changes non-linearly. This allows the memory state to be maintained with a very small steady-state current. Therefore.

The holding current when not selected is significantly lower than that shown in FIG. This has the advantage that the power consumption of the entire storage device can be reduced. However, transistors Ql and Q2 as switching elements and transistor Q3 . Both Q4s operate in deep saturation.

For this reason, the operational response of 5 to writing during selection tends to be slow. In other words, there was a drawback that the operating speed was slow.

As described above, in conventional storage devices, there is a trade-off between high operating speed and high current consumption, and low current consumption and slow operating speed. That was extremely difficult.

[Purpose of the invention]

An object of the present invention is to provide a storage device technology that can achieve both low power consumption and high speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by selectively using passive loads and active loads in memory cells of a memory device depending on whether they are selected or not, it is possible to achieve both low power consumption and high speed. It accomplishes its purpose.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 3 shows a memory cell of a memory device according to an embodiment of the invention.

The memory cell shown in the figure forms a type of bistable circuit, and is composed of two sets of switching elements and a load. NPN bipolar transistors Ql and Q2 are used as switching elements. Furthermore, two types of loads, active loads and passive loads, are used for each memory cell. The active load is a pnp bipolar transistor Q3. Q4 is used, and resistors R1 and R2 are used as passive loads.

The resistors R1 and R2 as passive loads are connected between the collectors of bipolar transistors Ql and Q2 as switching elements and the first word line W1, respectively.

Further, the pnp type bipolar transistor Q3. Q4 is n as the above switching element.
It is connected between the collectors of pn type bipolar transistors Ql and Q2 and the second word @W2. Furthermore, this p
np type bipolar transistor Q3. Q4 and above npn
The NPN bipolar transistors Ql and Q2 function as active loads whose equivalent load impedance changes depending on the conduction state of the npn bipolar transistors Ql and Q2 by connecting the base of one side and the collector of the other to each other. It's supposed to work. Furthermore, the npn type bipolar transistors Ql and Q2 as the switching elements each have two emitter electrodes. One emitter electrode of each 11' is a bit line Bl.

Connected to B2. Successive output or writing of memory data is
This is done via the bit lines B1 and B2. Further, the other emitter electrodes are commonly connected to each other and connected to the word return line C. A constant current circuit Isl for passing a holding current during non-selection and a constant current circuit Is2 for passing an operating current during selection are connected to this word return line C.

Next, its operation will be explained.

When the memory cell is not selected, the first word line W1 is in an inactive state of IILI+ (low level),
The second word, line W2, is in the active state II HII (high level). Therefore, in this non-selected state, the current supplied from the second word line W2 causes the pnP type bipolar transistors Q3. Only the active load due to Q4 functions as a load. This allows the storage cell to continue retaining its stored contents with very little retention current due to its active load.

Furthermore, when the memory cell is selected, the first word line WI is in an active state of it Hn (high level), while the second word line W2 is in an inactive state of IILl# (low level). Therefore, in this selected state, the current supplied from the first word line W1 causes the resistors R1 and R2 to
The passive load due to this will now function as a load. As a result, the memory cell operates at high speed in a non-saturated state (or in a low-saturated state) due to its passive load. This results in
Memory data in the memory cell can be rewritten at high speed.

As described above, by operating the memory cell with a passive load only when it is selected, and operating it with an active load when it is not selected, it is possible to increase the operating speed when it is selected, and The holding current can be made very small.

As a result, both low power consumption and high speed can be achieved.

Note that in the above embodiment, there are two word lines Wl.

W2 was selected and driven in a complementary manner.

However, only a very small holding current flows from the second word line W2. Therefore, the first word line W is selected.
1, and the second word line W2 may be fixed at a - constant level so that only the above-mentioned holding current continues to flow at all times.

Furthermore, as shown in FIG. 4, for example, Schmittkey barrier diodes DI and D2 for clamping may be connected in parallel to resistors R1 and R2 as passive loads, respectively. This causes the diode D1. ．． Due to the clamping effect of D2, the degree of desaturation of the npn bipolar transistors Ql and Q2 as switching elements is further increased, and the operating speed at the time of selection is further improved.

〔effect〕

(1) By providing two types of loads in each memory cell, active loads and passive loads, only the active load operates when not selected, and the passive load operates only when selected. The effect is that it is possible to achieve both lower power consumption and higher speed of the device.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the passive load may be one using an active element such as a transistor, or a diode.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to bipolar static RAM technology, which is the background field of application, but the invention is not limited thereto. It can also be applied to technology.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a passive load type memory cell used in a conventional memory device, FIG. 2 is a circuit diagram showing an example of an active load type memory cell used in a conventional memory device, FIG. 3 shows a storage device according to an embodiment of the present invention.
□Circuit diagram showing a memory cell used FIG. 4 is a circuit diagram showing a memory cell used in a memory device according to another embodiment of the present invention. W, Wl, W2... word line, Bl, B2... bit line, C... word return line, Ql, Q2... switching element (npn type bipolar transistor), R1,
R2...Passive load (resistance), 'Q3. Q4... Active load, Dl, D2... Schottky barrier diode for clamp, Isl, Is2... Constant current circuit. Figure 1 Figure 2 Figure 2
Figure 3 Figure 4

Claims (1)

[Scope of Claims] A memory device using a bistable circuit constituted by one or two sets of switching elements and a load as a memory cell,
The feature is that two types of loads are provided for each memory cell, an active load and a passive load, and only the active load is operated when not selected, and the passive load is operated only when selected. storage device. 2. An npn bipolar transistor is used as the switching element, and a pn bipolar transistor is used as the active load.
The memory device according to claim 1, characterized in that a p-type bipolar transistor is used.