JPS6151959A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6151959A
JPS6151959A JP59174371A JP17437184A JPS6151959A JP S6151959 A JPS6151959 A JP S6151959A JP 59174371 A JP59174371 A JP 59174371A JP 17437184 A JP17437184 A JP 17437184A JP S6151959 A JPS6151959 A JP S6151959A
Authority
JP
Japan
Prior art keywords
ion
source
forming
mixing
arsenic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59174371A
Inventor
Kazuhiko Hashimoto
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59174371A priority Critical patent/JPS6151959A/en
Publication of JPS6151959A publication Critical patent/JPS6151959A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To enable the titled device of complementary type to be manufactured by simple processes by a method wherein arsenic of large ion mass is used as the ion-mixing ion with respect to both of n-channel and p-channel in the process of ion mixing. CONSTITUTION:Impurity implanted layers 271 and 272 for forming the source and drain regions of an n-channel transistor are formed thinly, and impurity implanted layers 291 and 292 for forming the source and drain regions of a p- channel transistor are formed thinly. SiO2 films 301 and 302 are left on the side surfaces of gate electrodes 251 and 252. After formation of a molybdenum layer 31, arsenic for ion mixing is implanted over the whole surface; next, a resist pattern 32 is formed, and boron is ion-implanted with a mask of this pattern. With a molybdenum silicide pattern 31' left, the ions of the impurity implanted layers of the source and drain forming regiois are activated by heat treatment, thus forming source and drain regions 341, 342, 351, and 352. Using arsenic for ion mixing reduces the times of ion implantation by once.
JP59174371A 1984-08-22 1984-08-22 Manufacture of semiconductor device Pending JPS6151959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59174371A JPS6151959A (en) 1984-08-22 1984-08-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59174371A JPS6151959A (en) 1984-08-22 1984-08-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6151959A true JPS6151959A (en) 1986-03-14

Family

ID=15977441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59174371A Pending JPS6151959A (en) 1984-08-22 1984-08-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6151959A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656653A1 (en) * 1993-12-01 1995-06-07 AT&T Corp. Method of manufacturing shallow junction field effect transistor
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656653A1 (en) * 1993-12-01 1995-06-07 AT&T Corp. Method of manufacturing shallow junction field effect transistor
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process

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