JPS6150297A - メモリの使用方法 - Google Patents
メモリの使用方法Info
- Publication number
- JPS6150297A JPS6150297A JP60164121A JP16412185A JPS6150297A JP S6150297 A JPS6150297 A JP S6150297A JP 60164121 A JP60164121 A JP 60164121A JP 16412185 A JP16412185 A JP 16412185A JP S6150297 A JPS6150297 A JP S6150297A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- time
- during
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60164121A JPS6150297A (ja) | 1985-07-26 | 1985-07-26 | メモリの使用方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60164121A JPS6150297A (ja) | 1985-07-26 | 1985-07-26 | メモリの使用方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10669176A Division JPS5332634A (en) | 1976-09-08 | 1976-09-08 | Memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6150297A true JPS6150297A (ja) | 1986-03-12 |
JPS6242360B2 JPS6242360B2 (enrdf_load_stackoverflow) | 1987-09-08 |
Family
ID=15787145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60164121A Granted JPS6150297A (ja) | 1985-07-26 | 1985-07-26 | メモリの使用方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6150297A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6238598A (ja) * | 1985-08-12 | 1987-02-19 | Nippon Telegr & Teleph Corp <Ntt> | 自己訂正半導体メモリ |
EP1189234A1 (en) * | 2000-09-15 | 2002-03-20 | STMicroelectronics S.r.l. | Integrated electronic device with reduced internal connections |
-
1985
- 1985-07-26 JP JP60164121A patent/JPS6150297A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6238598A (ja) * | 1985-08-12 | 1987-02-19 | Nippon Telegr & Teleph Corp <Ntt> | 自己訂正半導体メモリ |
EP1189234A1 (en) * | 2000-09-15 | 2002-03-20 | STMicroelectronics S.r.l. | Integrated electronic device with reduced internal connections |
Also Published As
Publication number | Publication date |
---|---|
JPS6242360B2 (enrdf_load_stackoverflow) | 1987-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR910004188B1 (ko) | 반도체 기억장치 | |
US6122211A (en) | Fast, low power, write scheme for memory circuits using pulsed off isolation device | |
US6208168B1 (en) | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads | |
US6466511B2 (en) | Semiconductor memory having double data rate transfer technique | |
JP3866036B2 (ja) | 単一の入出力ピンによるマルチレベルデータの書込み及び読取りが可能な記憶集積回路 | |
US20010050866A1 (en) | Output circuit for alternating multiple bit line per column memory architecture | |
JPH01134790A (ja) | 半導体記憶装置 | |
US4667310A (en) | Large scale circuit device containing simultaneously accessible memory cells | |
JPH0114614B2 (enrdf_load_stackoverflow) | ||
KR910000388B1 (ko) | 메모리셀 블록의 선택적 동작이 가능한 반도체 메모리장치 | |
US4656613A (en) | Semiconductor dynamic memory device with decoded active loads | |
USRE38955E1 (en) | Memory device having a relatively wide data bus | |
KR960002815B1 (ko) | 분포된 데이타 라인 로딩을 사용하는 메모리와 그 메모리에서의 로드 배치 방법 | |
US5907509A (en) | Semiconductor memory device that can read out data at high speed | |
US5373470A (en) | Method and circuit for configuring I/O devices | |
JPS6150281A (ja) | メモリ | |
JPS6240800B2 (enrdf_load_stackoverflow) | ||
US5450566A (en) | Register block circuit for central processing unit of microcomputer | |
KR100240913B1 (ko) | 반도체 메모리 시스템, 프로그래머블 어레이 및 엑세스 시간 감소 방법 및 시스템 | |
JPS6150297A (ja) | メモリの使用方法 | |
JP2603145B2 (ja) | 半導体集積回路装置 | |
JPS6242359B2 (enrdf_load_stackoverflow) | ||
EP0533578B1 (en) | Semiconductor memory device enabling change of output organization with high speed operation | |
JPS6150300A (ja) | メモリ | |
JPH08138377A (ja) | 半導体記憶装置 |