JPS6149819B2 - - Google Patents

Info

Publication number
JPS6149819B2
JPS6149819B2 JP52086524A JP8652477A JPS6149819B2 JP S6149819 B2 JPS6149819 B2 JP S6149819B2 JP 52086524 A JP52086524 A JP 52086524A JP 8652477 A JP8652477 A JP 8652477A JP S6149819 B2 JPS6149819 B2 JP S6149819B2
Authority
JP
Japan
Prior art keywords
aperture
protective film
wiring path
bump
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52086524A
Other languages
English (en)
Other versions
JPS5421165A (en
Inventor
Masaharu Yorikane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8652477A priority Critical patent/JPS5421165A/ja
Priority to US05/925,324 priority patent/US4263606A/en
Publication of JPS5421165A publication Critical patent/JPS5421165A/ja
Publication of JPS6149819B2 publication Critical patent/JPS6149819B2/ja
Granted legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に外部配線と
の接続に金属の突起部（バンプ）を用いる半導体
装置に関する。
従来の半導体装置では、バンプは第１図ａ〜ｃ
に示すような構造が採られている。
即ち配線路１３を覆う保護膜１４に設けた開孔
１５〔第１図ａ〕に対して位置的に一致し寸法が
大きいバンプ１７がバリア（障壁）金属１６〔第
１図ｂ〕を界して形成されている〔第１図ｃ〕。
このバンプ１７と外部配線との接着時には、バリ
ア金属１６と接するバンプ１７の端部に集中した
応力が印加され、そのためバンプ１７の端部直下
を中心とした保護膜１４が破壊され易くその部分
での配線路１３の腐蝕が生じ信頼性上好ましくな
い。
本発明は、上記従来法の欠点を除き信頼性に優
れた半導体装置を提供することを目的とする。
本発明は、配線路表面の保護膜（電気絶縁膜）
に設けた開孔に対して位置的に一致し寸法の小さ
なバンプを形成することを特徴とする。
本発明によれば内部配線路上に設けた保護膜に
外部配線との接着時の応力が印加されず内部配線
金属を含む材料で応力が吸収されるため信頼性に
優れた半導体装置が得られる。
本発明の半導体装置の製造方法を実施例を用い
て説明する。第２図ａ〜ｄは本発明の一実施例を
示す製造工程図である。第２図ａを見ると、半導
体基板２１の一主面に被着させた電気絶縁膜２２
上に内部配線路２３を形成する。配線路２３は一
般にアルミニウムが用いられ、化学蝕刻法によつ
てパターン形成する。次に配線路２３を含む基板
２１表面に保護膜２４を被着し、所望の開孔２５
を設ける〔第２図ｂ〕。保護膜２４は配線路２３
の腐蝕及び欠損の防止を目的としシリコン酸化膜
が通常用いられ、その膜厚は5000Åが好適であ
る。次にMo、Ta、Ｗなどバリア（障壁）金属２
６を被着させ、前記開孔２５を覆うパターンを形
成する〔第２図ｃ〕。
一般にバリア金属は蝕刻が難しく、パターン形
成にはリフト・オフ法が好適である。
次にバンプ２７を形成する。このときバンプ２
７は前記開孔２５に対して位置的に一致し寸法が
小さいものとする。バンプ２７と外部配線との接
着に印加される応力はバリア金属２６と接するバ
ンプ２７の端部に集中するが、その端部は開孔２
５の内側に在るため、保護膜２４が破壊されるこ
とはない。
バンプ２７の膜厚は20μであり、金を用いてメ
ツキ法によるのが好ましい。バンプ２７はバリア
金属２６と接する位置に於いて、開孔２５に対し
て位置的に一致し寸法が小さければ良い、又バリ
ア金属２６は開孔２５での内部配線２３を保護す
ることともに、バンプ２７と内部配線２３が本実
施例のように異種金属の場合は相互拡散を防止す
るもので、その膜厚は2000Å程度が好適である。
以上本発明を実施例を用いて説明したが、本発
明の本質的部分は内部配線路の保護膜に設けた開
孔よりも小さな寸法のバンプを形成することにあ
り、目的は信頼性に優れた半導体装置を得ること
にあり、効果は内部配線が保護膜で覆われた耐蝕
性に優れた配線路が得られることにある。
【図面の簡単な説明】
第１図ａ乃至第１図ｃは従来技術による半導体
装置を製造工程順に示した断面図である。第２図
ａ乃至第２図ｄは本発明の一実施例を製造工程順
に示した断面図である。 尚、図において、１１，２１……シリコン基
板、１２，２２……シリコン酸化膜、１３，２３
……アルミニウム、１４，２４……シリコン酸化
膜、１６，２６……バリア金属、１７，２７……
金である。

Claims (1)

    【特許請求の範囲】
  1. １ 基板の一主面に形成された配線路と、該配線
    路を含む基板上に被着された絶縁保護膜と、該絶
    縁膜に対して前記配線路のコンタクト部が露出す
    るように設けた開孔部と、該開孔部内の露出され
    た部分および開孔周辺の絶縁保護膜をともに覆う
    ように前記開孔部から延在されたバリア金属膜
    と、前記開孔内に形成されたバリア金属膜が形成
    する新たな開孔底面の中央部のみに、かつ該新た
    な開孔の側面と接触することなく該開孔の高さよ
    り高く形成されたバンプ金属電極とを有し、該バ
    ンプ金属電極を外部配線と接続した時に、接続の
    応力が前記絶縁保護膜に印加されないようにした
    ことを特徴とする半導体装置。
JP8652477A 1977-07-18 1977-07-18 Semiconductor device Granted JPS5421165A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8652477A JPS5421165A (en) 1977-07-18 1977-07-18 Semiconductor device
US05/925,324 US4263606A (en) 1977-07-18 1978-07-17 Low stress semiconductor device lead connection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8652477A JPS5421165A (en) 1977-07-18 1977-07-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5421165A JPS5421165A (en) 1979-02-17
JPS6149819B2 true JPS6149819B2 (ja) 1986-10-31

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ID=13889366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8652477A Granted JPS5421165A (en) 1977-07-18 1977-07-18 Semiconductor device

Country Status (2)

Country Link
US (1) US4263606A (ja)
JP (1) JPS5421165A (ja)

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Also Published As

Publication number Publication date
US4263606A (en) 1981-04-21
JPS5421165A (en) 1979-02-17

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