JPS6148274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and relates to a structure that reduces variations in I _DSS characteristics and reduces low frequency noise of a junction field effect transistor (J-FET) formed on the same chip as a bipolar transistor. This is what you get. Furthermore, the present invention makes it possible to achieve the above object without increasing the types of power sources used.

Conventionally, when forming a J-FET on the same chip as a bipolar transistor, the surface of the gate region q in the semiconductor layer on the semiconductor substrate is A so-called back gate type is used in which a channel forming region ch is provided nearby, and the channel width is controlled via a pn junction on the back surface, thereby controlling the channel current. In this case channel area ch
has a SiO ₂ film formed on it, and Si−SiO ₂
It has the disadvantage that it is in contact with an interface and has a lot of noise due to surface states. In Figure 1a, G,
S and D are gate, source, and drain terminals, respectively.

In particular, the commonly used constants, for example, the impurity concentration in the channel region:
N _B = 4×10 ¹⁶ /cm ³ Thickness of SiO ₂ film directly above the channel: tox = 1000 Å Surface state density on the channel surface:
When N _SS =1×10 ¹¹ /cm ³ , the flat band voltage V _FB on the channel surface is V _FB = φ _MS −qN _ss /Cox = −0.60 + 0.40 − 0.47 = −0.67 V. However, Cox; SiO ₂ film capacitance , φ _MS ; This is the difference in work function between SiO ₂ and the semiconductor, and as shown in Figure 1b, when no bias is applied to the electrode on the channel, V _G =OV, and the channel surface has an accumulation ratio ( accumulation). For this reason, the channel current increases near the surface, and there is a tendency for more and more noise to be generated due to surface states and the like.
That is, FIG. 1b shows the relationship between the gate capacitance C of an electrode on SiO ₂ and the voltage V _M of this electrode, where is an inversion region, is a depletion region, and is an accumulation region.
As is clear from this figure, when the electrodes are normally installed, the capacitance is small in the accumulation region, which means that the channel current mostly flows on the surface.

The present invention is configured to reduce the channel current near the surface by applying a desired bias to an electrode provided on the channel region via an insulating film to bring the surface of the channel region into a depletion or inversion state. At the same time,
Furthermore, as a means for this purpose, a voltage suitable for integration into an integrated circuit is applied, and examples will be used below.
I will explain in detail.

FIG. 2a shows J- according to an embodiment of the present invention.
This shows the structure of FET. In Fig. 2, 1 is a self-excited oscillator, for example, the power supply voltage of an integrated circuit is applied to a power supply terminal 1', and a pulse is generated to a terminal 2 that goes back and forth between Vo and O as shown in the figure. The repetition frequency is approximately 1MHz.

The capacitor C ₁ and the diode D ₁ constitute a level shift circuit, and the potential at the junction between C ₁ and D ₁ is level-shifted to the negative side by Vo−V _D with respect to the terminal 2. Here, V _D is the forward rising voltage of the diode, and has a value of about 0.5V. Therefore, the intersection of C ₁ and D ₁ is a pulse that goes back and forth between V _D and V _D -Vo.

Diode D ₂ and capacitor C ₂ constitute a peak detection circuit, and terminal 3 holds the maximum value on the negative side of the pulse. In reality, the voltage drop due to _D2 is reduced by V _D , and the potential at terminal 3 is approximately -(Vo
−2V _D ). If we take the case where Vo is +5V, the potential of terminal 3 will be about -4V. 4 is a back-gate type J-FET having the same cross-sectional structure as the conventional one shown in FIG. has been done. 31 is a p-type gate region g, and 52 and 53 are both n ⁺ layer regions, which are source and drain regions, respectively. 61
is the formation region ch of the n-type channel, and the impurity concentration N _B is, for example, N _B =4×10 ¹⁶ /cm ³ 72 is a SiO ₂ film, and the film thickness t _px is, for example, t _px =
It is 1000Å. Reference numeral 82 denotes an electrode on the SiO ₂ film 72, and is made of aluminum, for example.

Now, if the surface state density N _ss at the interface between the channel forming region 61 and the SiO ₂ film 72 is N _ss =1×10 ¹¹ /cm ³ , then the flat band voltage V _FB is, as already explained, V _FB =−. In this embodiment, a negative voltage of -4V is applied to the electrode 82, and as shown in FIG. 1B, the surface of the channel is in a state of depression or impursion.

In this way, no current flows in the vicinity of the surface of the channel region, thereby suppressing the generation of noise caused by surface phenomena, thereby achieving low noise. Furthermore, according to the method of this embodiment, the power supply required for an integrated circuit in which a bipolar transistor and a J-FET are integrated is only Vcc, and only one positive power supply is required. A potential can be applied.

FIG. 2b shows a specific example of the structure when the portion after the terminal 2 in FIG. 2a is integrated with a semiconductor.
1 and the electrode 81 sandwiching the SiO ₂ film 71, the capacitance C ₁
is formed, a diode _D1 is formed by the n-type island 22 and the p-type region 42, a capacitance C2 is formed by the n-type island 23 and the p-type region 43, and a diode _D1 is formed by the n-type island 23 and the p-type region 43. ⁺ diffusion layer 51 forms a diode _D2 . The configuration in Figure 2b is 11, 24, 42.
It is a pnp transistor, 23, 43, 5
1 makes an npn transistor.

Therefore, the portion from terminal 2 to terminal 3 can be written as an equivalent circuit as shown in FIG. 2c.
In other words, both diodes D ₁ and D ₂ are actually transistors, and the collector current of the npn transistor Q ₂ also flows through the cathode side of D ₂ , but as long as the leakage current of each junction is sufficiently small. There is no problem. In addition, the capacitor C ₂ is formed by the base-collector junction of the transistor Q ₂ . According to the embodiment of FIG. 2b, the second
It will be appreciated that all of the components in Figure a are integrated within one chip. Note that it is well known that the self-excited oscillation circuit 1 having a repetition frequency of about 1 MHz is constructed in a monolithic manner, so the explanation is omitted.

The measurement results of the low frequency noise of the J-FET using the voltage V _M of the electrode 82 through the 1000 Å SiO ₂ film 72 on the channel forming region 61 as a parameter are shown in the third table.
As shown in the figure. The effectiveness of the present invention will be clear from this as well. In FIG. 3, the horizontal axis shows the frequency in Hz, and the vertical axis shows the noise voltage (nanovolt/√frequency).
As is clear from this, the present invention can exhibit excellent noise performance.

The above explanation was given assuming that Vo is constant, but the fourth
As shown in the figure, it is possible to determine Vo from the power supply Vcc by detecting the current of the standard measurement J-FETQ ₆ , which is built in the integrated circuit, and by using a circuit configured so that the value remains constant. . Hereinafter, an embodiment in which Vo is determined so that the I _Dss of the J-FET becomes constant will be described with reference to FIG. 4. R ₁ and R ₂ divide the integrated circuit power supply Vcc to create a reference voltage V _REF . Q ₃ and Q ₄ constitute a differential amplifier, R ₄ is a common emitter resistance, and R ₃ is a load resistance. Q ₅ is an emitter hole, and Q ₆ is an n with a negative bias potential applied to the electrode via an insulating film, similar to 4 in Figure 2 a.
-Channel J-FET, the gate is grounded along with the source. R ₅ is the load resistance of Q ₆ . In this circuit, an output voltage Eo is obtained at _Q5 , which is applied, for example, to terminal 1' in FIG. Note that in the normal self-excited oscillator 1, Vo=Eo.

Next, the operation of the circuit shown in FIG. 4 will be explained. now
If the current in Q ₆ , i.e. I _DSS , is larger than the desired value, the voltage drop across R ₅ will be large and the base voltage of Q ₄ will be lower than the base of Q ₃ , reducing the voltage drop across R ₃ and increasing the voltage drop across Q ₅ . Emitter voltage Vo increases. When Vo becomes high, 82
The absolute value of the negative voltage applied to the channel 61 also increases, and the width of the depletion layer on the surface of the channel 61 increases, reducing I _DSS . On the other hand, if I _DSS is smaller than the desired value, Eo (=Vo) becomes low, the absolute value of the negative voltage 82 also becomes small, and I _DSS increases. By using such a feed back circuit, it is possible to reduce the current near the surface of the channel to reduce noise and at the same time reduce the variation in I _DSS . That is, it is possible to correct wafer-to-wafer and lot-to-lot variations in _IDSS caused by variations in the diffusion process, etc., which is extremely useful in practice.

As understood from the above description of the embodiments, the following effects can be obtained according to the present invention.

(1) In back-gate J-FETs, low noise can be achieved by applying a voltage with the opposite polarity to the integrated circuit power supply to the electrode provided on the channel via an insulating film. .

(2) a voltage of the opposite polarity is generated within the integrated circuit;
No additional power supply is required. This is extremely convenient for integration and is a major feature of the present invention.

(3) By detecting I _DSS and the like and controlling the value of the voltage of the opposite polarity, it is possible to equalize the characteristic variations in I _DSS and the like.

(4) Performance can be improved without any change in the manufacturing process of the J-FET having the conventional structure shown in FIG. 1, which is convenient for integration.

As described above, the present invention provides a high-performance J-FET when integrated into a semiconductor integrated circuit in which a bipolar transistor is formed, for example.
-FET can be obtained without using any special manufacturing process, and no special power source is required, making a great contribution to this type of semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1a shows a conventional J-
A configuration diagram of the FET, FIG. 1b is a CV characteristic diagram for explaining the operation of FIG. 1a, and FIG. Fig. 2b is a structural diagram of a part of Fig. 2a as a semiconductor integrated circuit, Fig. 2c is an equivalent circuit diagram of a part of Fig. 2b, and Fig. 3 is an embodiment of Fig. 2a. FIG. 4 is a diagram showing the main circuit configuration of still another embodiment of the present invention. 1...Self-excited oscillator, _C1 , _D1 ...Capacitor and diode that constitute the level shift circuit, _C2 ,
D ₂ ...Capacitor that constitutes the peak detection circuit,
Diode, 22...n-type island, 31...p-type gate region, 43...p-type region, 51...n ⁺ diffusion layer, 52, 53...source, drain region, 61
...N-type channel forming region, 72...SiO ₂
Membrane, 82... Electrode, Q ₆ ... J-FET for measurement,
Vcc……Power supply voltage of integrated circuit.

Claims (1)

[Scope of Claims] 1. An electrode provided on a channel forming region formed on the surface of a gate region of a junction field effect transistor with an insulating film interposed therebetween, with an electrode opposite to the drain terminal of the transistor with reference to the source of the transistor. A semiconductor device characterized in that the vicinity of the surface of the channel forming region is brought into a depletion or inversion state by applying a polar voltage. 2. The semiconductor device according to claim 1, wherein the voltage of opposite polarity is obtained using a repeating signal generator, a level shift circuit, and a peak detection circuit. 3. The semiconductor device according to claim 1, wherein the characteristics of the junction field effect transistor are made uniform by controlling the value of the voltage of opposite polarity. 4. The semiconductor device according to claim 3, wherein the value of the voltage of opposite polarity is controlled by repeatedly changing the amplitude value of the signal. 5. The semiconductor device according to claim 3, wherein the value of the voltage of opposite polarity is controlled by detecting source and drain currents of a standard junction field effect transistor.