JPS6143058B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a personal portable heart rate monitor.

Traditionally, when a doctor examines you or an individual measures your heartbeat, you place the pad of your left thumb or index finger on the artery in your right wrist and apply pressure for 60 seconds, 10 seconds, or 6 seconds. It was common to know the heartbeat value or its approximate value by counting the pulse. In recent years, people of all ages have become active in exercise such as marathons and race walking for the purpose of personal health management, but this continues to put a strain on the heart, which can lead to extreme heart fatigue, especially in the elderly. To prevent this from happening, it is medically recommended to exercise at a heart rate Y that is suitable for each individual.

The present invention aims to provide a portable heart rate monitor that can measure the heart rate as described above at any time according to the individual's needs, for a short period of 1 to 2 seconds, and while continuing to exercise. The heart rate meter based on the present invention has each feature described in the claims, and one embodiment of the heart rate meter will be described in detail below.

FIG. 1 is a block diagram of the basic parts of the present invention. 100 is a stop control circuit, and this stop control circuit includes, for example, a signal frequency counter 18, a decoder 9, and a stop gate circuit 124.
Consists of. Further, the stop gate circuit 124 is composed of a plurality of stop gates and a multi-input stop gate. The first frequency divider group 101 is 4 in FIG.
A frequency divider group indicated by 7-1, 47, 49,
These include decoder 102 and decoders 48, 50, etc. in FIG. The second frequency divider group 201 is 41,4
2, 44, and 45 are shown. The third group of frequency dividers shows frequency dividers designated 37, 38, 65, etc. FIG. 2 is a circuit system diagram as an embodiment of the heart rate meter according to the present invention, in which 1 is a heart rate sensor section, 2
is a projector, 3 is a light receiver, 4 is an amplifier, 5 is an electric signal input, 6 is a low-pass filter, 7 is a pulse, 8
is a differentiator, 9 is a signal gate, 10 is a counting gate control binary, 11 is a preset gate,
12 is a green indicator light gate, 13 is a green indicator light, 14 is an inverter, 15 is a red indicator light gate, 16 is a red indicator light, 17 is a red display output terminal, 18 is a signal frequency counter, 19 is a decoder, 20 is a measurement Mode switch, 21 is a 1-period stop gate, 22 is a 2-period stop gate, 23 is a 3-period stop gate,
24 is a multi-input stop gate, 25 is a display timer, 25-1 is a timing resistor, 25-2 is a timing resistor, 26 is a reset gate each time, 27 is a display time control binary, 27-1 is a multi-input gate, 28 is a preset Range switch, 29
29-1 is a preset point switch, 29-1 is a preset memory, 30 is a preset decoder, 31 is a preset frequency divider, 32 is a clock oscillator, 33 is a clock frequency divider, 34 is an X1 clock gate, 35
is an X2 clock gate, 36 is an X3 clock gate, 37 is a 1/2 frequency divider, 38 is a 1/3 frequency divider, 39 is a clock multiple input gate, 40 is a timing gate, 41 is a 1/10 frequency divider, 42 is a 1/10 frequency divider, 43
is binary for Tu delay, 44 is 1/2 frequency divider, 4
5 is a 1/16 frequency divider, 46 is a decoder, and 47-1 is a 1/16 frequency divider.
2 frequency divider, 47 is 1/10 frequency divider, 48 is decoder,
49 is a 1/10 frequency divider, 50 is a decoder, 51 is an inverter, 52 is an inverter, 53 is a counting pulse configuration circuit, 55 is a NAND gate, 56-1 to 56-
14 is a NAND gate, 59 is a multi-input gate, 60
is a counting gate, 61 is a delay device, 62 is an auto-reset gate, 63 is a reset gate each time, 6
4 is a differentiator, 65 is a frequency divider, 66 is an up-down counter, 67 is an up-down control binary, 68 is a differentiator, 69 is a latch, 70 is a decoder, 71 is a scan control, 72 is a display, 73 is a constant Voltage circuit, 74 is a power switch, 7
5 is the battery, 76 is the power switch button ground, 7
7 indicates Tu delay switching terminals. Third
The figure is a circuit diagram as an example of the exchange voltage display of the battery voltage of the heart rate monitor according to the present invention, and FIG. This is a relationship diagram showing the fifth
The figure is a diagram showing the relationship between heart rate preset points and preset ranges of the heart rate monitor according to the present invention, and FIG. 6 is a diagram showing the relationship between display time and counting time of the heart rate meter according to the present invention. FIG. 7 is a pulse timing diagram in the circuit of FIG. 2.

Claim 1 relates to a means for counting heartbeats to be measured. Heart rate is usually measured by knowing the number of heartbeats every 60 seconds. That is, if PC is the heart rate and f is the frequency of the heart rate PC, the display will be PC=f×60...(a). Also, T is heart rate
If it is the period of PC, the display will be PC=60/T...(b).

The present invention aims to eliminate the time element of 60 seconds in the above equation and eliminate the reciprocal calculation of 1/T, thereby providing an economical personal heart rate monitor in a short time and in a relatively simple manner. It is. Theoretically, in order to directly read the heart rate PC, it is sufficient to set the period T of the heartbeat as the counting period, count the pulses of the period tc such that the counted value is equal to the heart rate PC, and display the pulses correspondingly.

That is, the corresponding expression is It is shown as PC=T/tc...(c).

Therefore, since PC=60/T and PC=T/tc according to the above equations (b) and (c), 60/T=T/tc. In other words, by using the period tc, it is possible to eliminate reciprocal calculations and directly read the heart rate with measurements that are not related to the time of 60 seconds. Naturally, the period tc is a variable number that changes depending on the heart rate. In other words, the relational expression between heart rate PC and its period T related to 60 seconds is
From PC=60/T, if we set PC=x and T=y, then
The change curve becomes x・y=60, and the relational expression between heart rate PC and period tc related to period tc is PC=T/tc
Similarly, if we set PC=x and tc=y, then x・y=T
get.

When applying the above theory to a specific counting circuit, it is necessary to first calculate the period T and determine the above-mentioned period tc before measurement, and then count the period T again using the period tc of the counting pulse. There is. In other words, let the period between the first and second beat of the heartbeat be the period T ₁ , know this T ₁ and determine the period tc, and let the period between the second and third beat be the period T ₂ , and set the period T ₂ . and count the pulses with period tc. Therefore, the measurement time is necessarily T ₁ +T ₂ , and the measurement time becomes long especially when the heart rate is low. Furthermore, since heartbeats often have arrhythmia, Ti=T ₂ may not be true and the measurement will not be accurate. The present invention shortens the measurement period of T ₁ + T ₂ by considering the measurement time in the case of such a low heart rate, and even if there is an arrhythmia, the period of the sampled heartbeat can be accurately measured, and the analog display can be directly read. Alternatively, it includes means for creating a digital cover. The measuring means of the present invention for achieving the above object will be explained below. First, the upper limit of the heart rate measurement range is set. That is, the minimum cycle Tu of heartbeats to be measured is set. tc starts in synchronization with the first beat of the heartbeat within a time period as explained below that is shorter than this minimum period Tu.
(o) Count pulses with a cycle such that the counted value becomes equal to the upper limit heartbeat value.
For example, if the arrival of the first beat is t=o and the upper limit heartbeat value is 200, the period of the upper limit heartbeat, that is, the minimum period Tu of the heartbeat, is Tu=300ms, and the count value for this period is 200. tc should be
(o) becomes tc(o)=1.5ms. Next, an UP/DOWN counting circuit is used for the counting circuit, and the above-mentioned counting pulse tc(o) is counted at UP, and the elapsed time after the period from O to Tu is sufficiently set at the lower limit of the heartbeat measurement range. Divide into several categories in advance until the period exceeds,
Set the required counting pulses for each category,
Then, sequentially until the second beat signal
The feature is that cumulative subtraction is performed in DOWN, and the cumulative subtraction value is made equal to the measured heart rate PC. In other words, divide the period TD that is longer than the interval between the first and second beats to be counted, and calculate TD=TD
(1)+TD(2)+TD(3)+...+TD(n),
PC={Tu/tc(o)}−{TD(1)/tc(1)}−………−
{TD(n)/tc(n)}. Of course, the counting field itself is an additive count during the period of Tu,
It is only necessary to switch to subtraction at the end of Tu. The present counting means is related to, and has been applied and developed, the principle of a heart rate measuring means for a heart rate monitor in Japanese Patent Application No. 52022/1987, which was previously filed by the present applicant.

Claim 2 is based on the above-mentioned instantaneous value measuring means in one cycle of the heartbeat, and it is based on the instantaneous value measuring means in one cycle of the heartbeat that each cycle of the heartbeat, such as between 3 or 4 beats, i.e., 2 cycles or 3 cycles, is caused by an arrhythmia. The present invention relates to a means for faithfully measuring the average value of the heartbeat, including the changes even if there are changes.

In other words, the period of the counting pulse is switched by the measurement mode switch based on the counting means in the case of one period measurement according to claim 1, and in the case of two period measurement, the third beat of the heartbeat or the third period. In the case of measurement, the same counting is performed except that counting is stopped at the fourth beat of the heartbeat. Therefore, for example, the period of the counting pulse in the case of two-cycle measurement is twice that of one-cycle measurement, that is, 2・tc(o), 2・tc(1), ...2・tc(n). The frequency divider that divides the periods and the frequency divider related to creating counting pulses are reset each time the second beat of the heartbeat arrives, and the count of the first period is calculated based on the interval between the first and second beats of the heartbeat. Counting in the second cycle is performed by continuing cumulative counting for two cycles between the second and third beats of the heartbeat in the same manner as in the one-cycle measurement described above,
When the third beat of the heartbeat arrives, counting is stopped at the signal of the third beat. In other words, the heart rate measurement value PC in this case is PC=[{Tu/2・tc(o)} −{TD(1)/2・tc(1)}−……− {TD(n)/2・tc( n)}] + [(Tu/2・tc(o)} −{TD(1)/2・tc(1)}−…… −{TD(n)/2・tc(n)}]… (d) In the above formula (d), the first term is the first and second beat of the heartbeat.
The second term is the count value between the beats, and the second term is the count value between the second and third beats, and the sum of the first term and the second term is the heartbeat count value obtained by two-cycle measurement. Now, if there is an irregular heartbeat and the period between the second and third beats becomes shorter than the period between the first and second beats, that is, the heart rate increases, then m If so, the second term of the above equation (d) is [{Tu/2×tc(o)}−
{TD(1)/2.tc(1)}−……−{TD(m)/2・tc
(m)}], the correct measured value of the second period can be obtained regardless of the first term of the above equation (d), and as a result, the above equation (d)
The sum of the first and second terms, that is, the measured value for two cycles can indicate the correct average value taking into account the arrhythmia of the heartbeat. In addition, in the case of 3-cycle measurement, the period of the measurement pulse is 3・tc(o), 3・tc(1)...3・
tc(n), the related frequency divider is reset for each heartbeat, and counting is stopped at the fourth beat to obtain the average value for three periods of the heartbeat. Note that the period Tu for addition, that is, up-counting, is described above as “Tu”.
"within a shorter period of time," but this is the period in question.
In determining the counting pulse tc(o) to be counted in Tu, it is possible to freely select a time shorter than an appropriate Tu in order to obtain a value that is relatively economical or required from the viewpoint of measurement accuracy. For example, if the upper limit of the measured heart rate value is 300, Tu = 200ms, and in one cycle measurement, tc(o) = 0.666...ms,
Also, to obtain 300 by reducing Tu=150ms, use tc(o)
= 0.5ms, and the latter is more economical.

Next, the presetting of the heart rate value according to claim 3 will be explained. In general, in sports medicine, the upper limit of optimal heart rate Y for athletes is ``Y = 180-
It is said to be around the age of 20. However, in reality, the Y value will be above or below depending on the amount of training and health condition of the individual, and will differ from person to person. Therefore, in the heart rate monitor according to the present invention, the Y value is preset, and when the Y value exceeds the preset value, a red display is displayed, and when the Y value is below the preset value, the heart rate monitor according to the present invention is intended for elderly people who require monitoring of the Y value. In this case, it is intended to cause a ``green display'' to be displayed. Generally, the preset value is displayed by extracting the corresponding value from the count value output of a counter, but since the display means according to the present invention has many control points, the preset value is displayed depending on the time period corresponding to the period of the heartbeat to be preset. It is characterized by display switching. In other words, the cycle range corresponding to the heartbeat to be preset within the heartbeat measurement range is defined as a preset range, the preset range is further divided into appropriate unit times, and preset points are defined. The preset range is a number of points. Therefore, if there is a second or subsequent heartbeat signal that matches the preset point within the preset range, each time it arrives and until the measurement ends, that is, In the case of 2-cycle measurement or 3-cycle measurement, the display will automatically switch to red or an alarm will sound until each cycle is completed, and the same will happen if the heart rate decreases and falls below the preset value. The display will automatically return to green. A summary of these related matters in the Examples is shown in FIG. 6 for reference.
It should be noted that the above-mentioned preset point includes the feature of making a specific setting by applying the above-mentioned Y value.
Next, automatic display time switching means will be explained.

Generally, the display time of the counted value is set to a certain value, but when counting and displaying based on the detected heart rate period as in this heart rate monitor, for example, the upper and lower limits of the heart rate value can be set. Comparing the displays, the closer you get to the upper limit, the longer the display time is than the counting time, and conversely, the closer you get to the lower limit, the longer the counting time is than the display time. This is not preferable in order to measure the heart rate in as short a time as possible, and in particular, the closer the upper limit is, the shorter the display repeat interval becomes, so a short display time is sufficient.
Furthermore, in order to reduce the current consumption of the power supply battery as much as possible, the display time for the count value on the lower limit side is
It is reasonable to appropriately shorten the display time on the upper limit side. As shown in Figure 6, the appropriate ratio between display time and counting time is determined by dividing the specific count value of 75.
This is set to about 0.6 to 0.7 seconds for 75 or less, and about 0.3 seconds for 75 or more, and this switching is automatically performed to solve the above-mentioned problem. An embodiment of the present invention described above is shown in FIGS.
This will be explained in detail with reference to FIGS. 4, 5, 6, and 7 to 17.

FIG. 2 is a block diagram of the circuit.
FIG. 7 is a pulse timing diagram in the circuit. In FIG. 2, 1 is a heartbeat sensor section, 2 is a light emitter of the sensor section, and 3 is a light receiver, and the output of the light receiver 3 is added to an amplifier 4. On the other hand, 5
is a similar electrical signal input. 6 is a low-pass filter that removes high-frequency noise components other than the signal; 7
is a pulser for amplifying the signal and pulsing the waveform. Now, when the first beat of the heartbeat is applied from the pulser 7 through the differentiator 8 and the signal gate 9 to the counting gate control binary 10 and the signal frequency counter 18, the counting gate control binary 10 is triggered, memorizes it, and outputs the signal frequency counter. At step 18, the first beat is counted and stored. The inverted output of the counting gate control binary 10 mentioned above opens the timing gate 40 and the counting gate 60 and resets the reset gate 2 each time.
6. Prepare to open the 1-period stop gate 21, 2-period stop gate 22, 3-period stop gate 23, ×1 clock gate 34, ×2 clock gate 35, and ×3 clock gate 36.
This will be described in the measurement mode described later.
When the measurement mode switch 20 is now in the position shown in FIG. 2, the one-period stop gate 21 and the x1 clock gate 34 will open when the inverted output of the counting gate control binary 10 described above is applied.

On the other hand, the clock oscillator 32 and its frequency divider 3
3 is already running, so its output clock pulse is applied to and passes through the x1 clock gate 34 and timing gate 40. The output of the timing gate 40 is applied to the next 1/10 frequency divider 42 via a 1/10 frequency divider 41. In this case, if you do not use the intermediate output, the corresponding 1/
The 10 frequency dividers 41 and 42 may be replaced with a frequency divided by 1/100. The intermediate output of the 1/10 frequency divider 42 is applied to the preset frequency divider 31, and the frequency divided output of the intermediate output in units of cycles is taken out as the output of the decoder 30. Specifically, in this embodiment, the period of the clock pulse is 0.5 ms, the output of the 1/10 frequency divider 41 is in 5 ms units, and the output of the next 1/10 frequency divider 42 is in 50 ms units. The intermediate output of the 1/10 frequency divider 42 is set to 10 ms. Therefore, the preset frequency divider 31 divides the frequency by pulses in units of 10 ms, and if the frequency divider 31 is decimal, the frequency is divided by pulses in units of 10 ms.
The output every 10 ms can be taken out as the output of the decoder 30 up to 100 ms, and this is repeated until it is reset.

On the other hand, the output of the 1/10 frequency divider 42 is added to the 1/2 frequency divider 44 and the Tu delay binary 43, and the output of the 1/2 frequency divider 44 is further added to the 1/16 frequency divider 45. The decoder 46 outputs the output pulses of the 1/2 frequency divider 44 sequentially in units of output pulse cycles. In this embodiment, the output of the 1/10 frequency divider 42 is
Since it is in 50ms units, binary 4 for Tu daylay
3 is after the first beat arrives, that is, when t=o
It is triggered after 50 ms have elapsed, and the inverted output of the binary 43 passes through the Tu delay switching terminal 77 and opens a NAND gate 55, which will be described later, after 50 ms has elapsed.
In this example, the clock pulse with a period of 0.5ms is
This occurs for 150ms until it is reset, and the UP counter counts 300.

This Tu delay switching terminal 77 is connected like the solid line connection shown in FIG.
If you change the connection like the dotted line connection of the delay switching terminal 77, the above-mentioned Tu delay binary 43
The output of is irrelevant, and the NAND gate 55 opens simultaneously with the arrival of the first beat so as to generate a counting pulse from t=o. In this embodiment, the 1/2 frequency divider 44 gives pulses of 100 ms to the 1/16 frequency divider, and the output of the decoder 46 is sequentially output in 100 ms units at the arrival of the first beat, that is, after t=o. will continue to occur until

Next, to explain the generation of counting pulses, as mentioned above, the clock pulse that has passed through the x1 clock gate 34 after the arrival of the first beat is applied to the 1/2 frequency divider 47-1 via the clock multiple input gate 39. /1
After passing through the 0 frequency divider, the decoder 48 outputs sequential outputs of twice the period of the clock pulse. Further, one of the intermediate outputs of the decoder 48 having a cycle corresponding to 20 times the cycle of the clock pulse is applied to the 1/10 frequency divider 49, and the output of the decoder 50 is divided into 20 times the cycle of the clock pulse. Obtain sequential output in units of twice the period. In this embodiment, since the clock pulse has a period of 0.5 ms, the output of the decoder 48 generates sequential outputs up to 10 ms in units of 1 ms, and repeats this process until it is reset. Also, the intermediate output of the decoder 48 is 10ms
The output of the decoder 50 is set to 1/10 and added to the 1/10 frequency divider 49, and the output of the decoder 50 generates sequential outputs up to 100 ms in units of 10 ms, and repeats the same process until it is reset. The necessary period of the counting pulse as an embodiment of the present invention can be determined from the relationship diagrams shown in FIGS. 4 and 8 between the measured heart rate value, the cumulative count value for that period, and the respective addition or subtraction values for each category. Accordingly, one period measurement is 0.5ms,
1ms, 2ms, 3.5ms, 5ms, 7ms, 9ms, 12ms,
32 ms, etc. are required, and in order to obtain these periodic pulses, in the embodiment, they are synthesized as shown in the following FIGS. 11 to 17.

FIG. 8 is a counting pulse distribution diagram for the entire counting period, where the Tu period is the addition period and the TD period is the subtraction period.

A counting pulse having a period of tc(o)=0.5 ms during the Tu period is obtained via an inverter 51 from the output of the clock multi-input gate 39 having the same period as the clock pulse. FIG. 9 shows the pulse timing diagram.

FIG. 10 shows a pulse timing diagram of the decoder 48 and decoder 50 outputs.

The counting pulse of tu(1) = 1ms period in TD(1) period is 1/2
It is obtained from the output of the frequency divider 47-1 via the inverter 52.

As shown in FIG. 11, the counting pulse configuration circuit 5
3(2) constitutes a counting pulse with a cycle of tc(2)=2 ms during the TD(2) period.

As shown in FIG. 12, the counting pulse configuration circuit 5
3(3) constitutes a counting pulse with a cycle of tc(3)=3.5 ms during the TD(3) period.

As shown in FIG. 13, the counting pulse configuration circuit 5
3(4) constitutes a counting pulse with a period of tc(4)=5ms during the TD(4) period.

As shown in FIG. 14, the counting pulse configuration circuit 5
3(5) constitutes a counting pulse with a period of tc(5)=5ms during the TD(5) period.

As shown in FIG. 15, the counting pulse configuration circuit 5
3(6), tc(6) of TD(6) period = tc(6) of 7ms period
= constitutes a counting pulse with a period of 7 ms.

As shown in FIG. 16, the counting pulse configuration circuit 5
3(7) constitutes a counting pulse with a period of tc(7)=9ms during the TD(7) period.

FIG. 17 shows a configuration diagram of counting pulses of periods tc(8) to tc(10) during periods TD(8) to TD(10).

Note that during the period TD(11) to TD(14), the counting pulses may be configured by the same means as described above, so the explanation will be omitted.

The counting pulse forming circuit 53 shown in FIG. 2 is a combination of counting pulse forming circuits 53(2) to 53(14).

Naturally, according to this synthesis means, if the input clock pulse is changed from 0.5 ms to 1 ms period, each of the above-mentioned composite values can be obtained as a pulse with twice the period, and from 0.5 ms to 1.5 ms. If the period is changed, a pulse with three times the period can be obtained in the same way. That is, when the measurement mode switch 20 is switched one step from the position shown in FIG. 2 to the 2-period measurement mode, the 2-period stop gate 22 is prepared to be opened, and the 1-period stop gate 21 is also prepared to be opened. The closed state changes to the closed state, and then ×2 clock gate 3
5 is opened and the ×1 clock gate is closed. Therefore, the output of the 1/2 frequency divider 37, which has been continuously driven by the output of the clock frequency divider 33, passes through the ×2 clock gate 35 and is output to the clock multi-input gate 39.
The signal is then added to the 1/2 frequency divider 47-1. Also,
Next, the measurement mode switch 20 is further switched one step in the same manner to set the 3-period measurement mode, and the 3-period stop gate 23 is similarly prepared to be opened, and the 2-period stop gate 22 is returned to the closed state, and then 3 clock gate 3
6 is opened and the ×2 clock gate is closed. Therefore, the output of the 1/3 frequency divider 38 passes through the ×3 clock gate 36 and the multiple clock input gate 39.
The signal is then added to the 1/2 frequency divider 47-1. In these 2-period measurements or 3-period measurements, the period of the clock pulse applied to the 1/2 frequency divider 47-1 is set to 2.
The operation itself is the same as in the case of one-period measurement, only by doubling or tripling it, so the following explanation will be continued for one-period measurement.

The pulses of each period obtained in this way are combined with the sequential output of the decoder 46 in units of 100 ms, and for example, in the period Tu, the 0th output of the decoder 46, that is, the 1/16 frequency divided vessel 45
During the period from t=o to 200ms obtained by the output in the state where is reset and the first output, NAND
In order to open the gate 55, in addition to one input of the NAND gate 55, a pulse of 0.5 ms period which is the output of the clock multi-input gate 39 mentioned above is applied.
It is added to the other input of the NAND gate 55. Therefore, the NAND gate 55 generates an output of 0.5 ms, which is applied to the counting gate 60 and passes through the multi-input gate 59 to the delay device 61 with an appropriate delay of, for example, 100 μs, and after this delay time, the output of the delay device 61 is output. is output and passes through the auto-reset gate 62 to the 1/2 frequency divider 47-1 and the 1/10 frequency divider 4.
7 and 1/10 frequency divider 49 are reset. Therefore, the first of the counting pulses applied to the counting gate 60
For example, 100μs after 0.5ms after t=o
It becomes a pulse of width and is added to the up-down counter 66, and counting of Tu periods to be added begins. However, in this embodiment, as mentioned above, this Tu period is
Since the NAND gate 55 is closed by the Tu delay binary 43 from 0 to 50 ms in order to set it to 150 ms, the 150 ms period from 50 ms to 200 ms becomes the Tu period, and within that period, for example, at a 0.5 ms period as described above. A count pulse train of 100 μs width is added and calculated by an up-down counter 66. Then 200ms to 300ms as the second output of the decoder 46
During the 100ms period until
It is applied as an output to a counting gate 60 and a delay device 61 via a multi-input gate 59, and is similarly auto-reset to repeat the signal with a period of 1 ms, for example, 100 μs.
Up-down counter 66 as a width counting pulse train
added to. At this time, the decoder 46
The up-down control binary 67 is triggered by the 200 ms leading edge transient of the second output between 200 ms and 300 ms, and the corresponding up-down counter 6
6 is controlled by subtraction counting, so after the relevant 200ms,
As the TD period, TD is calculated sequentially from the added value of the above Tu period.
Cumulative subtraction is made for each period segment.

In this way, in this embodiment, an additional value of 300 is obtained for the Tu period between 50 and 200 ms, and the TD period from the subsequent 200 ms until the arrival of the second beat is, for example, TD(1).
For the period between 200 and 300ms, subtract the count value 100, then 300
The values are subtracted and accumulated for each division period of sequential counting, such as obtaining a cumulative calculation value of -100=200. The count output of the up-down counter 66 is applied to a latch 69 and stored at one time.

Next, when the second beat arrives, the signal that has passed through the differentiator 8 passes through the signal gate 9 and enters the signal frequency counter 18.
is applied to the first output of the decoder 19, and outputs the arrival output of the second beat to the first output of the decoder 19, and the one-period stop gate 21
added to. As mentioned above, since the one-period stop gate 21 is already prepared to be opened by the mode switch 20, the output of the one-period stop gate 21 is immediately applied to the multi-input stop gate 24, and the output of the multi-input stop gate 24 is sent to the display timer. 25 and reset the counting gate control binary 10.
Also, the signal frequency counter 18 is reset. Therefore, the return output of the counting gate control binary 10 closes the counting gate 60, resets the preset memory 29-1, and closes each gate of the clock system and the reset gate 26 each time. On the other hand, the second heartbeat signal pulse that has passed through the differentiator 8 is also applied to the reset gate 26 each time.
Immediately before the gate control binary 10 is reset, the output of the reset gate 26 is obtained each time, and the up-down control binary 6 is
7, Binary for Tu delay 43, 1/10 frequency divider 4
5, 1/2 frequency divider 44, 1/10 frequency divider 42, preset counter 31, 1/10 frequency divider 41, differentiator 64, and each time through reset gate 63, display time control binary 27 , 1/2 frequency divider 47-1, 1/10 frequency divider 47, and 1/10 frequency divider 49, the first heart rate measurement is completed, and the second measurement preparation state is entered.

Note that when the above-mentioned display timer 25 is started,
Latch 69 is controlled to initiate the display and signal gate 9 closes to suppress the heartbeat signal until the display is terminated. Furthermore, the transient at the end of the operation of the display timer 25 passes through the differentiator 68 to reset the up-down counter 66 and simultaneously open the signal gate 9.

Here, the preset means will be explained.
As mentioned above, the preset referred to here means that the heart rate control value Y is determined in advance by the user himself.
It is a means of switching the indicator light to red from the edge or emitting an alarm sound such as a buzzer when the heart rate value is reached.

As mentioned above, the preset frequency divider 31 is 1/10
The frequency of the 10 ms period pulse, which is the intermediate output of the frequency divider 42, is divided by 1/10, and outputs are generated sequentially in units of 10 ms at the output of the decoder 30 of the preset frequency divider 31.

In this embodiment, as shown in FIG. 5, the 0th output of the decoder 30, the 1st output of 0 to 20ms,
2nd output and 3rd output of 40ms,... 80 in the same way
~100ms like 8th output and 9th output, 20ms
Each sequential output is set to a preset point, ,...
It is determined that Also, 300~ of the aforementioned decoder 46
The third output of 400 ms, the fourth output of 400 to 500 ms, and the fifth output of 500 to 600 ms are defined as preset, and, respectively, and any one of these is set by the preset range switch 28. For example, the preset point in the preset range is the detection point in the range of 580 to 600 ms, and the second beat of heartbeats that arrive within this range is 104 to 600 ms.
Equivalent to a heart rate value of 100. Also, for example, the preset point in the preset range is 300~
The range of 320 ms is the detection point, and the second heartbeat that arrives within this range corresponds to 200 to 190 beats. moreover,
The preset range incorporates the features of arranging specific preset points corresponding to the Y value mentioned above. In addition, the contact structure of the preset switch 29 that switches the preset point is such that when the preset point is advanced from preset to preset, etc., the preset point is switched in the order of... Therefore, the above-mentioned detection range will eventually be 500 to 600 ms when preset in the preset range, that is, a value corresponding to 120 to 100 of the heart rate value, and the value corresponding to the preset point in the preset range. The case includes features that can widen the detection band, such as 300 to 320 ms, or a value corresponding to a heart rate value of 200 to 190. In this way, the output of the preset switch 29 obtained from the preset setting point triggers the preset memory 29-1 and stores it.Furthermore, the inverted output of the preset memory is obtained, and this and the preset range switch 28 are used to trigger and store the preset memory 29-1. Set preset range output and preset gate 11
In addition to each input, the second beat and subsequent heartbeat signal pulses are added to another input of the preset gate 11, and the sum thereof is calculated to determine the maximum period within the preset range set. This is to switch the display of heartbeat signals that arrive within the range from this value to the set minimum value of the preset point from green to red. That is, when there is a sum output from the preset gate 11, the green indicator light 13 is lit by the green indicator light gate 12, which was previously ignited by the green indicator light gate 12 at the time of the first beat signal. The above-mentioned output closes the green indicator light gate 12 and also closes the red indicator light gate 1 via the inverter 14.
5 and therefore the second which comes within the preset range.
Depending on the heart rate signal and subsequent heartbeat signals, the display will be red until the first measurement is completed, that is, the second and third beats will be displayed in red when measuring two cycles, and the second, third, and fourth beats will be displayed in red when measuring three cycles. This is to light the lamp 16.

Note that the output of the red indicator light gate 15 is also taken out to the red indicator output terminal 17 and serves as a signal output for separately generating an alarm sound.

Since this heart rate monitor is portable, a battery 75 is used as the power source, which is supplied to each part through a constant voltage circuit 73.As mentioned above, when detecting a heartbeat, the power switch 74 is pressed with the tip of the thumb. The power is turned on when the power switch 74 is held between the pad of the tip of the index finger, etc. In particular, the push button surface of the power switch 74 is made of a conductive material, and the power switch button ground 76 is connected to the ground circuit of the sensor section 1. It has the feature that the body can be grounded automatically and with one operation during the above-mentioned clamping operation, and when detecting the heartbeat signal, it can effectively eliminate noise mainly induced by the commercial power frequency. This has the effect of ensuring stable counting.

Next, automatic display time switching will be explained.

As mentioned above, when the counting of the heartbeats is finished, the display timer 25 is triggered by the stop pulse from the multi-input gate 24 to start displaying the counted value, and the display is continued for a period of time determined by the operation timing of the display timer 25. The display is continued, and the display is ended when the display timer 25 is restored to operation. Normally, the above-mentioned operation timing is used with the timing resistor 25-1 of the timer 25 connected to the power supply voltage level Vcc, but in this embodiment, a separate timing resistor 25-2 is added to the timing resistor 25-1. are taken out in parallel or in series, and the timing resistor 25-2 is connected to the high-level output of the display time control binary 27, that is, approximately at the power supply voltage level, and the timing resistor 25-2 is connected so that the operating timing of the display timer is approximately 0.3 seconds. -1 and 25-2 are set.

Furthermore, the display time control binary 27
800ms to 1600ms from the 8th output of the decoder 46 mentioned above.
The 15th output for 800ms is connected to the multi-input gate 27-
Connect it to input 1. Therefore, the timing resistor 25-2 is connected to the seventh output of the decoder 46, that is, from 0 to 800 ms, regardless of the presence or absence of the detected signal.
During this period, the connection is maintained at high level "1" as described above, but at the eighth output of the decoder 46, the display time control binary 27 is triggered via the multi-input gate 27-1, and the binary 27 is inverted. The output switches and connects the timing resistor 25-2 to the "0" level, that is, approximately the ground potential. Therefore, the activation timing of the display timer 25 becomes larger than before, and the display time is reset to be relatively long, and up to the 15th output of the decoder 46.
This state is maintained for 800 to 1600ms, and this is repeated. In this way, the display is performed at one of the above-mentioned display times depending on the time at which the measured heartbeat signal arrives. In this embodiment, the above-mentioned automatic display switching time is set to a specific value of 75 for the heart rate to be measured, and the measurement range is divided into two, so that a heart rate of 75 or less is approximately 0.6 to 0.7 ms, or a heart rate of 75 or more is approximately 0.6 to 0.7 ms. Assuming 0.3ms, the ratio of display time/counting time is approximately 1/
2, that is, the former display time to the latter display time is equalized to 2:1. A diagram of these relationships is shown in FIG.

Next, it is inputted in a constant voltage circuit, a constant current circuit, or a power supply circuit having a series dropper.
Regarding the means for detecting and displaying the voltage at which the power supply battery that provides the input voltage of the power supply circuit should be replaced by using the output voltage difference, the power supply battery VB is connected to the input side of the power supply circuit 73 in FIG. The input divided voltage is divided by two resistors 77 and 78 at Vo.

Further, the output side of the power supply circuit 73 having an output voltage of Vcc is divided by two resistors 79 and 80, and the output divided voltage is set as Vs.

On the other hand, one transistor 81 having a sufficiently large emitter-base voltage is connected to the input division point, and its emitter is connected to the input division point, and one terminal of the transistor 81 is connected to the power supply circuit. Light emitting diode LED indicator 1 connected to 73 input or output voltages
6 through a required current limiting resistor 82 determined by Vo and VB or Vcc.

With this connection, the input dividing resistors 77 and 7
8 and the two output dividing resistors 79 and 80. When the above-mentioned VB decreases and reaches the voltage VB' that requires battery replacement, the voltage VB' decreases. The respective resistors 77, 78, 79 and This is an exchange voltage display means characterized by a resistance value of 80°, which is one of the features of this heart rate monitor, and can also be applied to general portable electronic devices. If the voltage polarity is reversed, you can change the transistor to a PNP type and slightly correct the resistance value.

[Brief explanation of the drawing]

FIG. 1 is a basic block diagram of the present invention. FIG. 2 is a circuit diagram as an embodiment of the heart rate monitor according to the present invention, and FIG. 3 is a circuit diagram as an embodiment of the battery voltage exchange voltage display of the heart rate monitor according to the present invention. FIG. 4 is a relational diagram showing the counting pulse period of the heart rate monitor according to the present invention, FIG. 5 is a relational diagram between heart rate value preset points and preset ranges of the heart rate monitor according to the present invention, and FIG. FIG. 2 is a diagram showing the relationship between display time and counting time of the heart rate monitor according to the invention. FIG. 7 is a pulse timing diagram in the circuit of FIG. 2.
FIG. 8 is a relationship diagram of each periodic pulse in the counting period. Figure 9 is a counting pulse timing diagram of the tc(o) period in the Tu period, and Figure 10 is the decoder 4.
Pulse timing diagram of 8,50 output, Figure 11 is
TC(2) cycle counting pulse configuration diagram, Figure 12 is TC(3) cycle counting pulse configuration diagram, Figure 13 is TC(4) cycle counting pulse configuration diagram, Figure 14 is TC(5) cycle diagram. Figure 15 is a counting pulse configuration diagram of tc(6) period, Figure 16 is a counting pulse configuration diagram of tc(7) period, and Figure 17 is tc(8) to tc(10) period. FIG. 3 is a counting pulse configuration diagram. 1... Heart rate monitor, 100... Stop control circuit,
18... Signal frequency counter, 9... Decoder, 1
24...stop gate circuit, 10...counting gate control binary, 60...counting gate,
66... Up-down counter, 67... Up-down control binary, 72... Display, 2
0... Counting mode switcher, 32... Clock oscillator, 101... First frequency divider group, 102... Decoder, 201... Second frequency divider group, 46... Decoder, 53... Counting Pulse configuration circuit, 59...gate circuit, 61...delay circuit, 62...reset circuit.

Claims (1)

[Claims] 1. A heart rate sensor section, an up-down counter,
a display, a clock oscillator, a first frequency divider group that divides the frequency of the clock pulse that is the output of the clock oscillator, and a first frequency divider group that outputs the output of the first frequency divider group as a plurality of types of counting pulses. a decoder, a second frequency divider group that divides the frequency of the clock pulse, a second decoder that outputs the output of the second frequency divider group as a different output for each counting period, and first and second decoder outputs. a gate circuit that outputs a corresponding counting pulse for each of the counting division periods; a counting gate control binary that detects the signal from the heart rate sensor; and a gate circuit that receives the output of the counting gate control binary and the output of the gate circuit a counting gate that outputs counting pulses to the up-down counter; and an up-down control that controls addition and subtraction of the up-down counter based on a signal from the heart rate sensor and a signal of a predetermined division period from the second decoder. A heart rate monitor comprising a binary signal and a stop control circuit that detects a signal from a heart rate sensor section and controls an up-down counter to stop, and outputs the output of the up-down counter to a display. 2. A counting mode switch that switches depending on the number of heartbeats to be measured, and a third frequency divider group that is switched by the counting mode switch between the clock oscillator and the first frequency divider group. A stop control circuit includes a signal frequency counter that counts and stores signals from the heart rate sensor section, a stop gate circuit that is switched by the counting mode switch, and a stop control circuit that corresponds to the number of heartbeats to be measured based on the output of the signal frequency counter. It is composed of a decoder that outputs an output to a stop gate circuit, and when a signal that is one heartbeat higher than the predetermined number of heartbeats to be measured is received, the up-down counter's counting is stopped by the output of the stop gate circuit, and the up-down count is displayed on the display. The heart rate monitor according to claim 1, wherein the heart rate monitor is configured to display the organ output. 3 Heart rate sensor section, up-down counter,
a display, a clock oscillator, a first frequency divider group that divides the frequency of the clock pulse that is the output of the clock oscillator, and a first frequency divider group that outputs the output of the first frequency divider group as a plurality of types of counting pulses. a decoder, a second frequency divider group that divides the frequency of the clock pulse, a second decoder that outputs the output of the second frequency divider group as a different output for each counting period, and first and second decoder outputs. a counting gate control binary that detects the signal from the heart rate sensor section, a gate circuit that outputs a corresponding counting pulse for each counting division period; and a counting gate control binary that detects the signal from the heart rate sensor section; a counting gate that outputs counting pulses to the counter; and an up-down control binary that controls addition and subtraction of the up-down counter based on the signal from the heart rate sensor section and the signal of a predetermined division period of the second decoder. In a heart rate monitor that includes a stop control circuit that detects a signal from a heart rate sensor section and controls an up-down counter to stop and outputs the output of the up-down counter to a display device, the second decoder output can be counted multiple times. A preset range switch that determines one of the division periods, and a preset counting division period of the preset decoder output from the second frequency divider group through the preset frequency divider are divided into several division periods. A preset point switch that defines one preset point within a subdivision, an indicator light, and an output corresponding to a predetermined counting segment period of the second decoder through a preset range switch and a preset point switch that passes through the preset point switch. 1. A heart rate monitor comprising: a preset gate that controls display operation of said indicator light by supplying an output corresponding to a preset point determined from said preset decoder.