JPS61285770A - Diffused semiconductor element - Google Patents

Diffused semiconductor element

Info

Publication number
JPS61285770A
JPS61285770A JP60127501A JP12750185A JPS61285770A JP S61285770 A JPS61285770 A JP S61285770A JP 60127501 A JP60127501 A JP 60127501A JP 12750185 A JP12750185 A JP 12750185A JP S61285770 A JPS61285770 A JP S61285770A
Authority
JP
Japan
Prior art keywords
layer
gate
implanted
junction fet
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60127501A
Other languages
Japanese (ja)
Inventor
Koji Suzukawa
鈴川 光二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60127501A priority Critical patent/JPS61285770A/en
Publication of JPS61285770A publication Critical patent/JPS61285770A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

Abstract

PURPOSE:To obtain a diffused type semiconductor element characterized by high amplitude, high withstanding voltage and high current, by providing an MOSFET, providing an offset gate type junction FET, which is continued to the MOSFET, providing a longitudinal junction FET, which is continued to said junction FET, and reducing gate capacity. CONSTITUTION:Boron is implanted in semiconductor substrates 9 and 10, and a P<+> layer 11 is formed. Then, boron is implanted in a forming region of a layer 12, and a P layer 12 is formed. Thereafter, a gate insulating film is formed, and a gate electrode 17 is formed thereon. With the electrode 17 as a mask, arsenic is implanted, and an N<-> layer 14 is formed. Phosphorus is implanted in a forming region of a layer 13, and nan N layer 13 is formed. Then, phosphorus is diffused, and layers 15 and 18 are formed. Thereafter electrodes 16 and 19 are taken out. At this time, since the gate 17 is not formed on each junction FET, the gate capacity becomes small. This structure has a two-stage cascade form of an FET2 and an FET3, and gm becomes large in an FET1.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は拡散量Mos(o−Mos)pET(電界効果
トランジスタ)を構成する拡散型半導体素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a diffused semiconductor element constituting a diffused Mos (o-Mos) pET (field effect transistor).

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

この種の拡散型半導体素子の従来構成を第7図に示し、
その電気的等価回路を第8図に示す。図中1はN型高濃
度不純物層を形成する半導体基板、2はN型低濃度不純
物層を形成する半導体基板、3はP+拡散層、4はペー
ス拡散層、5はソース拡散層、6は絶縁膜、7は電極、
8はゲート電極である。第8図のトランジスタFET+
は層2.4.5の部分で形成され、トランジスタFET
 Zは層1.2.4の部分で形成される。
The conventional structure of this type of diffusion type semiconductor element is shown in FIG.
The electrical equivalent circuit is shown in FIG. In the figure, 1 is a semiconductor substrate on which an N-type high concentration impurity layer is formed, 2 is a semiconductor substrate on which an N-type low concentration impurity layer is formed, 3 is a P+ diffusion layer, 4 is a pace diffusion layer, 5 is a source diffusion layer, and 6 is a semiconductor substrate on which an N-type high concentration impurity layer is formed. Insulating film, 7 is an electrode,
8 is a gate electrode. Transistor FET+ in Figure 8
is formed in layer 2.4.5 and is a transistor FET
Z is formed in part of layer 1.2.4.

入力信号はゲート Gに供給され、ドレインD。The input signal is supplied to the gate G and the drain D.

ソース8間電流は層1−2−4−5−電極7と −流れ
る。
Current flows between the source 8 and the layers 1-2-4-5 and the electrode 7.

第7図のものは、ペースを形成するとき、第9図に示す
ようにゲート8をマスクにペース拡散(2層4)を行な
い・ペースのサイド広がりを利用してゲート部を形成す
る。構造的にはカスケード構造により、FET 1でg
−を大きくしく増幅)、FET、で高耐圧化する特徴を
有する。
In the case shown in FIG. 7, when forming the paste, the paste is diffused (two layers 4) using the gate 8 as a mask, as shown in FIG. 9, and the gate portion is formed using the side spread of the paste. Structurally, due to the cascade structure, FET 1 has a
- is greatly amplified), FET, and has the feature of high breakdown voltage.

このとき、上記の如くダートをマスクにサイド広がり拡
散を利用しているため、構造上ダート面積が大きくなり
、つまり容量Can (1’ −)8の中間部分での容
量)及びCog(?−)−gの縁部での容量)が大きく
なる。これにより素子を回路上に組み込みをした場合、
高周波においてr−ト容量を駆動するため余分な電力が
必要となる。またスレッシ、ルド電圧コントロールとし
て、ダートをマスクにソース拡散をしてr層5を形成し
、そのサイド広がりをコントロールしてスレッシ、ルド
電圧をコントロールしている。
At this time, since side spread diffusion is used using the dart as a mask as described above, the dart area becomes large due to the structure, that is, the capacitance Can (1'-)capacitance at the middle part of 8) and Cog(?-) - the capacitance at the edge of g) increases. When this element is incorporated into a circuit,
Extra power is required to drive the r-to-capacitor at high frequencies. In addition, for threshold and lead voltage control, source diffusion is performed using the dirt as a mask to form an r layer 5, and the side spread of the r layer 5 is controlled to control the threshold and lead voltages.

これは製造中の拡散ばらつきkより、スレッシ曹ルド電
圧が変化しやすくなるものである。
This is because the threshold voltage changes more easily than due to diffusion variations during manufacturing.

〔発明の目的〕[Purpose of the invention]

本発明は上記実情に鑑みてなされたもので、前記従来の
問題点を改善し得る拡散型半導体素子を提供しようとす
るものである。
The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a diffusion type semiconductor element that can improve the above-mentioned conventional problems.

〔発明の概要〕[Summary of the invention]

本発明は、MOSFETと、これにつづくオフセットゲ
ート型ジャンクションFETと、これkつづ〈縦型ジャ
ンクシ、 7 FETとを具備し、前記MOSFETの
e−)は前記各ジャンクシ、ンFET上には設けられな
いようにしたものである。
The present invention comprises a MOSFET, an offset gate type junction FET following the MOSFET, and a vertical type FET, and the MOSFET e-) is provided on each junction FET. I tried to avoid it.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例を説明する。第1
図は同実施例の構成を示す断面図、第2図はその電気的
等価回路である6図中9はN型高濃度不純物層を形成す
る半導体基板、10はN型低濃度不純物層を形成する半
導体基板、JlはP+拡散層、12はペース拡散層、1
3はソース拡散1tl、J 4はオフセットr−ト層、
Jsはソース拡散層、16は電極、17はff−)電極
、18はr拡散層、19は電極、2oは絶縁。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view showing the configuration of the same embodiment, and Figure 2 is its electrical equivalent circuit. 9 in 6 figures is a semiconductor substrate on which an N-type high concentration impurity layer is formed, and 10 is a semiconductor substrate on which an N-type low concentration impurity layer is formed. Jl is a P+ diffusion layer, 12 is a pace diffusion layer, 1
3 is the source diffusion 1tl, J4 is the offset r-t layer,
Js is a source diffusion layer, 16 is an electrode, 17 is an ff-) electrode, 18 is an r diffusion layer, 19 is an electrode, and 2o is an insulation.

膜である。第2図のトランジスタFET1は層14゜1
2.15の部分で形成され、縦型ジャンクシ1ントラン
ジスタFET、は層12,10.9の部分で構成され、
オフセットy−トmジャンクショントランジスタpgr
s&4層24の部分で構成される。入力信号はゲートG
1/c供給され、ドレインD、ソース8間電流は、層9
−10−21−電極19一層1g−14−12−15−
電極16と流れる。
It is a membrane. The transistor FET1 in FIG. 2 has a layer 14°1.
2.15, the vertical junction transistor FET is formed of layers 12, 10.9, and
offset y-to-m junction transistor pgr
It is composed of the s&4 layer 24 part. The input signal is gate G
1/c and the current between the drain D and the source 8 is the layer 9
-10-21-Electrode 19 single layer 1g-14-12-15-
It flows with the electrode 16.

第1図の裂造工程例としては、半導体基板9゜J 01
1CN o y t l 〜20 X 10”/cm2
打ち込み、P+層11を形成する0次に層12の形成予
定領域Ic f o 7 f 5〜20 X 10”7
cm2打チ込ミ、2層12を形成する。その後f−)絶
縁膜を形成し、その上にゲート電極17を形成し、これ
をW ス/ K砒素f:5〜50 X 10”/32打
ち込み1N一層14を形成する。また層13の形成予定
領域に燐を5〜50 X 10”/cm2打ち込み、N
層ノ3を形成する。次に燐を1〜2 X 10” 3−
5拡散し、層15.38を形成する。その後電極16 
、19の取り出しを行なうものである。
As an example of the fabrication process shown in FIG. 1, the semiconductor substrate 9°J 01
1CN o y t l ~20 X 10”/cm2
Planned area for implantation and formation of zero-order layer 12 to form P+ layer 11 Ic f o 7 f 5~20 x 10”7
Form 2 layers 12 with a cm2 punch. After that, f-) an insulating film is formed, a gate electrode 17 is formed thereon, and a 1N layer 14 is formed by implanting W/K arsenic f: 5 to 50 x 10"/32. Also, a layer 13 is formed. Inject 5 to 50 x 10"/cm2 of phosphorus into the planned area and apply N
Form layer No. 3. Next, add phosphorus to 1~2 x 10” 3-
5 to form layer 15.38. Then the electrode 16
, 19 are taken out.

第1図のものは、ゲート17が各ジャンクシ1ンFET
上に形成されないから、ダート容量が小となっている。
In the one in Fig. 1, the gate 17 is connected to each junction FET.
Since dirt is not formed on top, the dirt capacity is small.

また第2図に示されるように、構造はFET 鵞とFE
T 3の2段カスケード構造となる。
Also, as shown in Figure 2, the structure is FET and FE.
It has a two-stage cascade structure of T3.

FET、でg。を大きくする(増幅)役目をする。FET, g. It plays the role of increasing (amplifying).

pg’rsで高耐圧化し、FET 、でFET 、を動
作させる中耐圧の素子である( FET、 、 FET
、 Kも耐圧をもたせた)、これによりFET、で低耐
圧とし、gfIlt−大きくすることができる。goは
g。=W/L (Wはゲート幅、Lはゲート長)で示さ
れ、ゲート長りを小さくするとgrnが上がる。このと
き素子製造上、耐圧が低くなる欠点がある。この耐圧を
補なう役目として、FET sのオフセットゲートFE
Tで耐圧をかせぐものである。これにより従来型の特長
である大電流、高耐圧化と、本発明の特長である低f−
)容量化が実現できるものである。まえ本構造はペース
拡散孔部の表面を利用するため、ペース表面濃度でMO
SFETのスレッシ、ルド電圧が簡単に設定できるもの
である。、第3図は第1図の変形例であり、FET、の
部分金素子内忙埋込んだ形としたものである。その他の
構成は第1図のものと略対応するの−で、゛対応個所に
は同一符号を付して説明を省略する。
It is a medium-voltage element that has a high breakdown voltage with pg'rs and operates a FET (FET, , FET).
, K also has a withstand voltage), this allows the FET to have a low withstand voltage and to increase gfIlt. go is g. =W/L (W is gate width, L is gate length), and as the gate length is reduced, grn increases. At this time, there is a drawback in manufacturing the device that the withstand voltage becomes low. To compensate for this breakdown voltage, the offset gate FE of FET s
T is used to increase the withstand pressure. This makes it possible to achieve both the large current and high withstand voltage that are the features of the conventional type, and the low f-
) Capacity can be realized. Since this structure utilizes the surface of the paste diffusion hole, the MO at the paste surface concentration is
The SFET threshold and field voltage can be easily set. , FIG. 3 is a modification of FIG. 1, in which the gold element of the FET is partially embedded. The other configurations substantially correspond to those in FIG. 1, so corresponding parts are designated by the same reference numerals and description thereof will be omitted.

第4図、II!、6図は第3図の配線金属層3σを省略
した変形例で、第6図ではかつ第1図の層1391Bを
省略し、層14で代用している。
Figure 4, II! , 6 is a modification in which the wiring metal layer 3σ of FIG. 3 is omitted, and in FIG. 6, the layer 1391B of FIG. 1 is omitted and layer 14 is substituted.

第5図は第1図の変形例で、これと導電型を逆にしても
本発明を適用できることを示したものである。第5図に
おいて第1図と対応する個所には同一符号を用い、かつ
これにダッシュを付しておく。
FIG. 5 is a modification of FIG. 1, and shows that the present invention can be applied even if the conductivity type is reversed. In FIG. 5, the same reference numerals are used for parts corresponding to those in FIG. 1, and a dash is added thereto.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明忙よれば、従来の間散聾半導体
素子が提供できるものである。
As explained above, according to the present invention, a conventional semiconductor device for intermittent deafness can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す断面図、第2図はその
等価回路図、第3図ないし第6図は本発明の異なる実施
例を示す断面図、第7図は従来のD−MO8素子を示す
断面図、第8図はその等価回路図、第9図は同素子の濃
度分布図である。 9.10・・・半導体基板、Jl・・・P拡散層、 1
2・・・ベース拡散層、13・・・ソース拡散層、14
−・・オフセットゲート層、15・・・ソース拡散層、
16、J9・・・電極、17・・Qゲート電極、1g・
・・N+拡散層、FETt =MO8F:ET、 FE
Tz ”・縦型yヤンrシ、ンFET%FET s・・
・オフセットゲート型ジャンクションFET 。 出願人代理人 弁理士 鈴 江 武 彦U)  −一 普爾
FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, FIGS. 3 to 6 are sectional views showing different embodiments of the present invention, and FIG. 7 is a conventional D - A sectional view showing an MO8 element, FIG. 8 is an equivalent circuit diagram thereof, and FIG. 9 is a concentration distribution diagram of the same element. 9.10...Semiconductor substrate, Jl...P diffusion layer, 1
2... Base diffusion layer, 13... Source diffusion layer, 14
-...offset gate layer, 15...source diffusion layer,
16, J9...electrode, 17...Q gate electrode, 1g.
・・N+diffusion layer, FETt = MO8F:ET, FE
Tz ”・Vertical type
・Offset gate type junction FET. Applicant's agent Patent attorney Suzue Takehiko U) - Ippuji

Claims (2)

【特許請求の範囲】[Claims] (1)MOSFETと、これにつづくオフセットゲート
型ジャンクションFETと、これにつづく縦型ジャンク
ションFETとを具備したことを特徴とする拡散型半導
体素子。
(1) A diffused semiconductor device characterized by comprising a MOSFET, an offset gate type junction FET following it, and a vertical junction FET following it.
(2)前記MOSFETのゲートは前記オフセットゲー
ト型ジャンクションFET及び縦型ジャンクションFE
T上に設けられていないことを特徴とする特許請求の範
囲第1項に記載の拡散型半導体素子。
(2) The gate of the MOSFET is the offset gate type junction FET and the vertical type junction FE.
2. The diffusion type semiconductor element according to claim 1, wherein the diffusion type semiconductor element is not provided on the T.
JP60127501A 1985-06-12 1985-06-12 Diffused semiconductor element Pending JPS61285770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60127501A JPS61285770A (en) 1985-06-12 1985-06-12 Diffused semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60127501A JPS61285770A (en) 1985-06-12 1985-06-12 Diffused semiconductor element

Publications (1)

Publication Number Publication Date
JPS61285770A true JPS61285770A (en) 1986-12-16

Family

ID=14961531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60127501A Pending JPS61285770A (en) 1985-06-12 1985-06-12 Diffused semiconductor element

Country Status (1)

Country Link
JP (1) JPS61285770A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0654827A1 (en) * 1993-05-26 1995-05-24 Texas Instruments Incorporated Integrated power cascode
WO1995018465A1 (en) * 1993-12-28 1995-07-06 North Carolina State University Three-terminal gate-controlled semiconductor switching device with rectifying-gate
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5488236A (en) * 1994-05-26 1996-01-30 North Carolina State University Latch-up resistant bipolar transistor with trench IGFET and buried collector
WO2003012996A1 (en) * 2001-07-23 2003-02-13 Siced Electronics Development Gmbh & Co Kg Switching device for a switching operation at a high working voltage
JP2013526129A (en) * 2010-04-07 2013-06-20 エー・テー・ハー・チューリッヒ Switching device having a series arrangement of JFETs

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5786619A (en) * 1988-02-25 1998-07-28 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
EP0654827A1 (en) * 1993-05-26 1995-05-24 Texas Instruments Incorporated Integrated power cascode
WO1995018465A1 (en) * 1993-12-28 1995-07-06 North Carolina State University Three-terminal gate-controlled semiconductor switching device with rectifying-gate
US5488236A (en) * 1994-05-26 1996-01-30 North Carolina State University Latch-up resistant bipolar transistor with trench IGFET and buried collector
WO2003012996A1 (en) * 2001-07-23 2003-02-13 Siced Electronics Development Gmbh & Co Kg Switching device for a switching operation at a high working voltage
US6822842B2 (en) 2001-07-23 2004-11-23 Siced Electronics Development Gmbh & Co. Kg Switching device for switching at a high operating voltage
JP2013526129A (en) * 2010-04-07 2013-06-20 エー・テー・ハー・チューリッヒ Switching device having a series arrangement of JFETs

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