JPS61282911A - Input device - Google Patents
Input deviceInfo
- Publication number
- JPS61282911A JPS61282911A JP60123604A JP12360485A JPS61282911A JP S61282911 A JPS61282911 A JP S61282911A JP 60123604 A JP60123604 A JP 60123604A JP 12360485 A JP12360485 A JP 12360485A JP S61282911 A JPS61282911 A JP S61282911A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- input device
- cut
- electrodes
- electrode terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 238000001514 detection method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 101100008048 Caenorhabditis elegans cut-4 gene Proteins 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100008049 Caenorhabditis elegans cut-5 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔発明の属する利用分野〕 本発明は、高精度の入力装置に関する。[Detailed description of the invention] [Field of application to which the invention pertains] The present invention relates to a high precision input device.
従来のこの種装置は、入力装置上の押下点の位置を高精
度に検出する際、入力装置を構成している2枚の基板上
の電極の抵抗値が完全に均一であることが必要であった
。しかし、この基板上の電極の抵抗値を完全に均一にし
ようとするには、電極の膜厚を完全に一定することが必
要であるが、電極の製造上、これは実際には不可能であ
った。In conventional devices of this type, when detecting the position of a pressed point on an input device with high precision, it is necessary that the resistance values of the electrodes on the two substrates that make up the input device be completely uniform. there were. However, in order to make the resistance value of the electrodes on this substrate completely uniform, it is necessary to make the film thickness of the electrodes completely constant, but this is actually impossible due to the manufacturing of the electrodes. there were.
よって、このような従来の入力装置にあっては、基板上
の電極の抵抗値を全面に渡って均一に形成する事ができ
ないため、押下点の位置を高精度に検出する事ができな
いという問題点があった。Therefore, in such conventional input devices, the resistance value of the electrode on the board cannot be formed uniformly over the entire surface, so there is a problem that the position of the pressed point cannot be detected with high precision. There was a point.
本発明はこのような従来の問題点を解決するためになさ
れたもので、基板上の電極の抵抗値が全面に渡って均一
でなくても、押下点の位置を高精度に検出できることを
目的としている。The present invention was made to solve these conventional problems, and its purpose is to be able to detect the position of a pressed point with high precision even if the resistance value of the electrode on the substrate is not uniform over the entire surface. It is said that
表面にほぼ均一に電極を形成し、該電極の両端に電極端
子を有する2枚の基板を、前記電極面を対向するように
し、かつ前記電極端子を交差する方向に合わされた入力
装置を構成し、前記電極端子間における、入力装置とし
ての有効エリア外において、前記電極に切れ目を入れる
事により、前記電極端子間の抵抗値を変化させ、前記電
極間の抵抗均一性を向上させる。An input device is constituted by two substrates having electrodes formed almost uniformly on their surfaces and having electrode terminals at both ends of the electrodes, with the electrode surfaces facing each other and aligned in a direction that intersects the electrode terminals. By making cuts in the electrodes outside the effective area as an input device between the electrode terminals, the resistance value between the electrode terminals is changed and the resistance uniformity between the electrodes is improved.
本発明の作用を図面に基づいて詳細に説明する。第1図
は、本発明の基本構造を示す。The operation of the present invention will be explained in detail based on the drawings. FIG. 1 shows the basic structure of the invention.
第1図(α)において、切れ目4により、電極端子3間
の電極2の抵抗を補正する。第1図(B)に、補正の原
理を示す。電、!2は、第1図(B)のR1−R6と分
割して考えられ、切れ目4により、J=J=・・・R,
=R,となるようにするわけである。すなわち、電極2
を、複数のブロックに分割し、その面積変化により、各
ブロック抵抗値を、変化させ、補正する。In FIG. 1 (α), the resistance of the electrode 2 between the electrode terminals 3 is corrected by the cut 4. FIG. 1(B) shows the principle of correction. Electric! 2 can be considered by dividing it into R1-R6 in FIG. 1(B), and by the cut 4, J=J=...R,
=R. That is, electrode 2
is divided into a plurality of blocks, and the resistance value of each block is changed and corrected by changing the area.
次に各ブロックの面積変化率の算出し方について説明す
る。第2図に示す、dl 。dl、・・・dk・・・d
、・・・d が、各ブロックである。電極端子外+1
3間に、電圧Vを印加し、電極2上の電位を第2図の様
に(s X s )ケ所測定する。各fxラインの平均
電位は、
欝も
・・・・・・(1)
と表わされ、まず(’Is’!・・・・・・V%〕を求
める。次に各ブロックの理論電圧降下VTRは、と表わ
せれる。また、各ブロック電圧降下vdxは、
u d J: v −v x ・・・−・−
(8)!−1
と表わされ、次に理論電圧1)THとの差を算出する。Next, a method of calculating the area change rate of each block will be explained. dl shown in FIG. dl,...dk...d
,...d are each block. A voltage V is applied between +1 and 3 outside the electrode terminals, and the potential on the electrode 2 is measured at (s x s) locations as shown in FIG. The average potential of each fx line is expressed as (1) First, find ('Is'!...V%]. Next, the theoretical voltage drop of each block. The VTR can be expressed as follows.In addition, each block voltage drop vdx is as follows: u d J: v − v x ・・・−・−
(8)! -1, and then calculate the difference from the theoretical voltage 1) TH.
v (dx−va)= adz−v!n =(4)
(4)式で求めたv(dx−tH) の最大値のブロッ
クを最大抵抗値ブロックとして、他のブロック抵抗値を
、その最大抵抗値にするため、以下の計算をする。最大
値ブロックの電圧降下をv d maxとすると、
となる。すなわち、各ブロックの面積を、Pの割り合い
で小さくすれば、電極端子3間の抵抗は均一に近づく。v (dx-va)=adz-v! n = (4)
The block with the maximum value of v(dx-tH) determined by equation (4) is set as the maximum resistance value block, and the following calculations are performed to set the resistance values of the other blocks to their maximum resistance values. If the voltage drop of the maximum value block is v d max, then the following equation is obtained. That is, if the area of each block is reduced by the ratio of P, the resistance between the electrode terminals 3 approaches uniformity.
以下、本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
(実施例1)
第3図は、上基板にFFfT(1B8μ)フィルム、下
基板にガラス(1,1t ) 、電極に蒸着工TO9電
極端子にへ?ペースト、を使用し、電極工TOへ切れ目
をレーザー(ヤング)より入れ、電圧検出型入力装置を
試作した。上基板と下基板の間には、数十μのスペーサ
を置き、四方向にはシール接着剤を配した。基板サイズ
は、約1100X150であり、切れ目は、20 mm
Pitchで第3図の様に有効エリア外、電圧印加方
向2ケ所に入れた。レーザースポット径は、約25μで
行った。抵抗均一性は、この補正により格段に良くなり
、未処理時における測定電位と理論電位の差は、1/3
以下になった。また、直線性誤差的に考える未処理時2
−4%が、17%に補正された。この入力装置を、12
8X256ドツト(ドツトピッチ147° )の液晶表
示モジー−ル上に設置し、ドツト対応動作されたところ
、未処理時、抑圧下ズレ上5ドツトのものが、補正後、
±2ドツトに補正された。(Example 1) Figure 3 shows an FFfT (1B8μ) film on the upper substrate, glass (1,1T) on the lower substrate, and vapor deposition on the electrode TO9 electrode terminal. Using paste, a cut was made in the electrode TO using a laser (Young), and a voltage detection type input device was prototyped. A spacer of several tens of microns was placed between the upper and lower substrates, and sealing adhesive was placed on all four sides. The board size is approximately 1100 x 150, and the cut is 20 mm.
As shown in Figure 3, the pitch was placed at two locations outside the effective area in the voltage application direction. The laser spot diameter was about 25μ. The resistance uniformity is significantly improved by this correction, and the difference between the measured potential and the theoretical potential when untreated is reduced to 1/3.
It became below. Also, considering the linearity error when unprocessed 2
-4% was corrected to 17%. This input device is 12
When installed on a liquid crystal display module with 8 x 256 dots (dot pitch 147°) and operated with dot support, the one with 5 dots above the suppression deviation when unprocessed, but after correction,
Corrected to ±2 dots.
(実施例2)
実施例1における切れ目ピッチを5wmにして同様の補
正を行ったところ、抵抗均一性は、実施例1以上に良く
なり、直線性誤差で、1.9%がa、5%にできた。(Example 2) When the same correction as in Example 1 was made by changing the cut pitch to 5 wm, the resistance uniformity was better than that in Example 1, and the linearity error was 1.9% a, 5% I was able to.
(実施例5)
実施例1における、切れ目ピッチをα3mmにして同様
の補正を行りたところ、抵抗均一性は、実施例2以上に
良くなり、直線性誤差で、2.0%が、Q、4%にでき
た。この場合レーザによる切れ目は、階段上から、はぼ
曲線になり、fl/p時は、コンビエータ制御により、
簡単に行なえるであろうなお、本発明の入力装置を、電
圧検出型のかわりに電流検出型としてもよい。また、基
板は、透明でも、不透明でも良く、電極も同様である。(Example 5) When the same correction as in Example 1 was made with the cut pitch set to α3 mm, the resistance uniformity was better than that in Example 2, and the linearity error was 2.0%, which was , 4%. In this case, the cut by the laser becomes a curved line starting from the top of the stairs, and at fl/p, the cut is made by the combiator control.
It should be noted that the input device of the present invention may be of a current detection type instead of a voltage detection type, which may be easily implemented. Further, the substrate may be transparent or opaque, and the same applies to the electrodes.
またレーザーによる切れ目は、エツチングでも、カッタ
ー等によるものでも、同様の効果が実現できる。Furthermore, the same effect can be achieved by making cuts by laser, by etching, by using a cutter, etc.
以上説明したように本発明は、基板上の電極抵抗体の不
均一から生ずる位置検出の誤差が補正され、高精度の位
置検出が可能となった。また、基板上の電極抵抗体を均
一に形成するという、製造上難かしいことを、工程中に
レーザ等で、切れ目を入れるという方法に変える事がで
き、高精度の入力装置を提供することが容易になった。As explained above, according to the present invention, errors in position detection caused by non-uniformity of electrode resistors on a substrate are corrected, and highly accurate position detection becomes possible. In addition, the difficult manufacturing process of uniformly forming electrode resistors on the substrate can be replaced with a method of making cuts using a laser or the like during the process, making it possible to provide a highly accurate input device. It got easier.
第1図は、本発明の基本構造、第2図は、本発明の実行
例、第3図は、本発明の入力装置の実施例における入力
部、を示す。
1・・・・・・・・・基 板
2・・・・・・・・・電 極
5・・・・・・・・・電極端子
4・・・・・・・・・切れ目
5・・・・・・・・・有効エリア境界線6・・・・・・
・・・電流測定点
である。
以上FIG. 1 shows the basic structure of the present invention, FIG. 2 shows an implementation example of the invention, and FIG. 3 shows an input section in an embodiment of the input device of the invention. 1...... Substrate 2... Electrode 5... Electrode terminal 4... Cut 5... ...... Effective area boundary line 6...
...It is a current measurement point. that's all
Claims (2)
電極端子を有する2枚の基板を、前記電極面を対向する
ように配し、かつ前記電極端子が交差する方向に合わさ
れた入力装置を構成し、前記電極に切れ目を入れ、該切
れ目により前記電極の、前記電極端子間の抵抗値を変化
させ構成されたことを特徴とする入力装置。(1) Two substrates having electrodes formed almost uniformly on their surfaces and having electrode terminals at both ends of the electrodes are arranged so that the electrode surfaces face each other, and the electrode terminals are aligned in a direction to intersect. What is claimed is: 1. An input device comprising: a cut in the electrode; and a resistance value between the electrode terminals of the electrode is changed by the cut.
しての有効エリア外に前記切れ目を入れた事を特徴とす
る特許請求の範囲第1項記載の入力装置。(2) The input device according to claim 1, wherein the cut is made outside an effective area as an input device with a width of several tens of microns to several hundred microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60123604A JPS61282911A (en) | 1985-06-07 | 1985-06-07 | Input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60123604A JPS61282911A (en) | 1985-06-07 | 1985-06-07 | Input device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61282911A true JPS61282911A (en) | 1986-12-13 |
Family
ID=14864721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60123604A Pending JPS61282911A (en) | 1985-06-07 | 1985-06-07 | Input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61282911A (en) |
-
1985
- 1985-06-07 JP JP60123604A patent/JPS61282911A/en active Pending
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