JPS61265660A - Execution mode switching control system in multiprocessor system - Google Patents

Execution mode switching control system in multiprocessor system

Info

Publication number
JPS61265660A
JPS61265660A JP10772785A JP10772785A JPS61265660A JP S61265660 A JPS61265660 A JP S61265660A JP 10772785 A JP10772785 A JP 10772785A JP 10772785 A JP10772785 A JP 10772785A JP S61265660 A JPS61265660 A JP S61265660A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
processor
system
virtual address
address mode
subprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10772785A
Inventor
Masafumi Tsuru
Original Assignee
Toshiba Comput Eng Corp
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To avoid troubles due to a difference between execution modes in each processor by providing a memory where flag information showing the presence or absence of the package of a subprocessor and a temporary memory area in which information on system is saved and stored is allocated and stored.
CONSTITUTION: When a device is turned on, an IPL and a test program, both of which are stored in a ROM 6, are activated, and the package state of the subprocessor 2 is checked. When it is packaged, a register MSW showing the state of a processor in a main processor 1 is set. After a system is initialized, an operation system OS is loaded in a system RAM 7 from a floppy disk 8. When the necessity of switching the operation in a virtual address mode occurs, the OS activates a superviser to check an MSW in the processor 1. When a subprocessor flag is set, the operation is switched in a virtual address mode in accordance with the instruction of the processor 2. Afterward, the processor 1 initializes for execution in a virtual address mode, and is switched in a virtual address mode.
COPYRIGHT: (C)1986,JPO&Japio
JP10772785A 1985-05-20 1985-05-20 Execution mode switching control system in multiprocessor system Pending JPS61265660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10772785A JPS61265660A (en) 1985-05-20 1985-05-20 Execution mode switching control system in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10772785A JPS61265660A (en) 1985-05-20 1985-05-20 Execution mode switching control system in multiprocessor system

Publications (1)

Publication Number Publication Date
JPS61265660A true true JPS61265660A (en) 1986-11-25

Family

ID=14466415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10772785A Pending JPS61265660A (en) 1985-05-20 1985-05-20 Execution mode switching control system in multiprocessor system

Country Status (1)

Country Link
JP (1) JPS61265660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372578A2 (en) * 1988-12-09 1990-06-13 Tandem Computers Incorporated Memory management in high-performance fault-tolerant computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372578A2 (en) * 1988-12-09 1990-06-13 Tandem Computers Incorporated Memory management in high-performance fault-tolerant computer system

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