JPS61253863A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the variation of noise characteristics and current amplification factors, by providing emitter and collector regions having a conductivity type opposed to that of a semiconductor substrate, on the bottoms of two or more recesses provided on the surface of the substrate. CONSTITUTION:An N<+> type base electrode lead-out region 7 is provided in an appropriate part on an epitaxial layer 3 outside a collector region 6. The surface of the device is protected by a silicon oxide film. A vertical NPN transis tor and the like are provided in the other island regions in the epitaxial layer 3. A P-type emitter region 5 and the P-type collector region 6 are formed simul taneously with the formation of the base of the NPN transistor. Carriers injected from the emitter region 5 to the epitaxial layer 3 reach the collector region 6 through the epitaxial layer 3 between the recessed portions. Accordingly, these carriers hardly pass through the surface of the epitaxial layer 3 having a higher interfacial level. Accordingly, a higher current amplification factor can be obtained with little variation and the noise characteristics can be im proved remarkably.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a lateral transistor, and particularly relates to a current amplification factor (
This invention relates to a lateral transistor with high hPII (hereinafter referred to as hPII) and excellent noise characteristics.

[Conventional technology]

NPN) transistors and PN in bipolar integrated circuits
P) Mixed use of transistors has advantages such as increased freedom in design and simplification of circuit configuration, and lateral transistors are generally well known.

Horizontal PNP) transistors are usually vertical NPN) -
It is formed as shown in the schematic cross section of FIG. 2 by utilizing the base diffusion of the transistor. That is, after forming an N-type epitaxial layer 3 on a P-type semiconductor substrate 1 having an N+-type buried layer 2 and forming a P-type insulation isolation region 4, an NPN)
At the same time as forming the base of the transistor, an emitter region 5 and a collector region 6 surrounding it are formed simultaneously, and further N
It is made by forming the N+ type space electrode lead-out region 7 at the same time as forming the emitter of the PN) transistor.

A silicon oxide film 8 is formed on the surface for surface protection.

[Problem that the invention seeks to solve]

In such a conventional lateral transistor, carriers injected from the emitter region 5 are transferred to the epitaxial layer 3.
through the surface of the collector region 6. Since the surface of the epitaxial layer 3 is directly under the oxide film 8, there is a thermally strained layer generated during the oxidation and heat treatment steps, and
It has many interface states due to the uneven distribution of impurities.

Such interface states promote trapping, re-emission, and recombination of carriers passing through the epitaxial a3 surface. When carrier traps occur, the collector current fluctuates, degrading the noise characteristics, and when carriers are re-emitted or recombined, the base current increases and h□ decreases. Furthermore, since it is difficult to control the interface states on this surface during the manufacturing process, there is a drawback that it is difficult to suppress noise characteristics and variations in h and H.

[Means for solving problems]

In order to eliminate such drawbacks, the present invention aims to prevent carriers injected from the emitter region from conducting through the semiconductor substrate surface.
This is an improved version that allows conduction inside the semiconductor substrate.

That is, according to the present invention, the 2
At the bottom of the one or more recesses, an emitter region and a collector region of the conductive plate opposite to the semiconductor body are provided.

〔Example〕

The present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of a lateral PNP transistor according to the present invention. The same parts as in the conventional example shown in FIG. 2 are given the same numbers. Note that the electrodes and the openings in the oxide film are omitted. In other words, an N-type epitaxial layer 3 is formed on a P-type semiconductor substrate 1 having an N+-type buried layer 2, and this N-type epitaxial layer 3 is divided into many island regions by a P+-type insulating isolation region 4. Separated. Two or more recesses are provided in one island region of the N-type epitaxial layer 3 by etching. The recesses are formed, for example, so that one recess surrounds another recess in an annular shape. A P-type emitter region 5 and a collector region 6 are formed at the bottom of each recess by diffusion. At this time, emitter region 5
and the collector region 6 are not formed in one recess. The recess can be easily formed, for example, by using an oxide film as a mask on the epitaxial layer 3 whose main surface is the crystal plane (100), and employing anisotropic etching with an alkaline etching solution such as KOH, if desired. can.

In this case, the (100) plane is deeply etched and a flat (111) plane with a predetermined angle is obtained on the side surface of the recess. An N+ type base electrode lead-out region 7 is provided in the epitaxial layer 3 at a suitable position outside the collector region 6, and the surface is protected with a silicone oxide film 8. A vertical NPN transistor and the like are formed in other island regions of the epitaxial layer 3, and the emitter region 5 and collector region 6 are formed simultaneously with the formation of the base of the NPN transistor. The pace electrode lead region 7 is also formed at the same time as the emitter of the NPN transistor is formed.

According to this embodiment, carriers injected into the epitaxial layer 3 from the emitter region 5 pass through the epitaxial layer 3 between the recesses and reach the collector region 6, so that the carriers pass through the surface of the epitaxial layer 30, which has many interface states. The reliability is small, so the noise characteristics are good, and go/<
It is possible to obtain a lateral transistor that does not cause ruts.

〔Effect of the invention〕

As explained above, according to the present invention, the conventional horizontal PN
P) Compared to transistors, high hFK can be obtained with less variation, and noise characteristics are also significantly improved.

Note that the present invention is not limited to the above embodiments, and even if the polarity is changed, the scope of the present invention does not depart from the scope of the present invention.

[Brief explanation of the drawing]

1 is a sectional view schematically showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view schematically showing an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N+ type buried layer, 3... N-type evaporative layer, 4...
... P type insulation isolation region, 5 ... P type emitter region, 6 ... P type collector region, 7 ...
...N+ type base electrode extraction area, 8...
Silicon oxide film. %1 Figure Z

Claims (1)

[Claims] A semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, a first recess formed on the surface of the semiconductor layer, and a second recess of the opposite conductivity type formed at the bottom of the first recess. 1 region, a second recess formed on the surface of the semiconductor layer laterally apart from the first recess, and a second recess of the opposite conductivity type formed at the bottom of the second recess. and the first area.
and a semiconductor active element is formed using the second region.