JPS61246860A - Interruption control system - Google Patents

Abstract

PURPOSE:To shorten the time when interruption is accepted by identifying the peripheral device which requests the interruption when an interruption control means receives a microinterruption request signal and reporting the effect to a processor. CONSTITUTION:An interruption controller 7 is provided which transmits cyclically a device number put previously to the peripheral device 2 to other peripheral devices 2 at every certain period. Each peripheral device 2 collates an interruption permitting device number Ne transmitted from the interruption controller 7 with the device number Ns given to itself. When they are equal, the interruption request signal Q is transmitted to the interruption controller 7 if necessary. Receiving the interruption request signal Q from the peripheral device 2, the interruption controller 7 fixed the device number transmitted to each peripheral device 2 to the device number of the peripheral device 2 transmitting the interruption request signal Q, and simultaneously transmits the device number Ns of the peripheral device transmitting the interruption request signal Q and the interruption request signal Q to the microprocessor 1. Thus the time necessary for accepting the interruption can be shortened, and a load caused by the interruption processing of the processor can be reduced.

Description

[Detailed Description of the Invention] [Summary] In a processing device that controls a plurality of peripheral devices, a device number assigned to each peripheral device is periodically transmitted to the peripheral devices, and each peripheral device receives the time when it receives its own device number. By sending an interrupt request signal to the area, the processing device can immediately identify the peripheral device that is the source of the interrupt request, thereby reducing the interrupt processing load.

[Industrial application field]

The present invention relates to an improvement in an interrupt control method in an information processing device including a processing device and a plurality of peripheral devices.

A known interrupt function is used as a means for notifying a processing device that controls a plurality of peripheral devices of, for example, the end of an operation from the peripheral device side. For peripheral devices, it is desired that the time required for an interrupt to be accepted by a processing device be as short as possible, and for the processing device, it is desirable that the load due to such interrupt processing be reduced as much as possible.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional interrupt control method.

In FIG. 3, among the plurality of peripheral devices 2 controlled by the microprocessor 1, the peripheral device 2 that requests an interrupt from the microprocessor 1 sends an interrupt request signal Q to the signal line 3. When the microprocessor l receives the interrupt request signal Q transmitted from the peripheral device 2 via the signal line 3, it interrupts the process being executed and then sequentially sends an interrupt to the signal line 4 leading to each peripheral device 12. A timing signal E is sent. Each peripheral device 2 to which the interrupt interval signal E has been transmitted stops the interrupt request signal Q that is currently being sent to the signal wA3, and also switches the signal line 5, the device number N assigned to the own device is sent. The microprocessor 1 is connected to each peripheral device until the device number N is returned from the signal line 5! Sequentially sends the interrupt interval signal E to the signal vA4 leading to 2,
By returning the device number N from the signal line 5, the peripheral device 2 that is the source of the interrupt request is identified, and necessary information is transmitted and received to and from the peripheral device 2 via the signal f%16.

[Problem 3 to be Solved by the Invention] As is clear from the above explanation, in a conventional interrupt control system, the microprocessor 1, which has received the interrupt request signal Q, sequentially issues an interrupt interval to each peripheral device 2. The signal E was transmitted and the presence or absence of an interrupt request was searched. Therefore, it takes a lot of time to accept an interrupt, and the microprocessor 1
There was a risk that the processing capacity would be overwhelmed.

[Means for solving problems]

The present invention solves the above problems by taking the following measures.

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, an interrupt control device 7 is provided which cyclically transmits a device number assigned to each peripheral device 2 in advance to each peripheral device 2 at a constant period.

Each peripheral device 2 receives an interrupt request signal Q in the time domain to which the device number assigned to the device itself is transmitted from the interrupt control device 7.
is transmitted to the interrupt control device 7.

The interrupt control device 7 that has received the interrupt request signal Q from the peripheral device 2 fixes the device number to be transmitted to each peripheral device 2 to the device number of the peripheral device 2 that sent the interrupt request signal Q, and also performs processing. The interrupt request signal Q and the device number N of the peripheral device that sent the interrupt request signal are transmitted to the device 1.

[Effect]

That is, according to the present invention, upon receiving an interrupt request signal, the interrupt control means immediately identifies the interrupt requesting peripheral device, and directs the requesting peripheral device, which has been identified as having generated an interrupt request, to the processing device. Notice.

As a result, the time it takes to accept an interrupt is significantly shortened.
Furthermore, the load associated with interrupt processing on the processing device is significantly reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an interrupt control method according to an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, an interrupt control device 7 is provided between the microprocessor 1 and each peripheral device 2. In FIG.

In FIG. 2, each peripheral device 2 is assigned a unique device number Ns.

The control unit 71 in the interrupt control device 7 sets the selection unit 72 to select the counting unit 73, and then starts the counting unit 73. The counting section 73 advances at a constant cycle and sends the counted value to the signal line 8 via the selection section 72 as the interrupt permission device number Ne. The interrupt permission device number Ne is transmitted to each peripheral device 2 via the signal vA8.

Each peripheral device 2 is connected to the interrupt controller 7 via the signal &18.
The interrupt permission device number No. transmitted from Ns is the own device number Ns.
If they match, an interrupt request signal Q is sent to the signal line 3 as necessary. The interrupt request signal Q is transmitted to the interrupt control device 7 via the signal line 3.

In the interrupt control device 7, when the interrupt request signal Q is transmitted from the signal line 3, the interrupt permission device number N of the register 74 is set.
It is stored at the address specified by e.

Furthermore, the control unit 71 causes the counting unit 75 to step at a constant cycle,
The count value is set as the interrupt acceptance device number Na and transmitted to the register 4, and the interrupt request signal Q stored at the address specified by the interrupt acceptance device number Na is scanned.

When the interrupt request signal Q is extracted from the address specified by the interrupt reception device number Na, the control section 71 stops the counter section 75 from walking, and the extracted interrupt request signal Q and the counter section 75 output the interrupt request signal Q. The interrupt accepting device number Na is transmitted to the microprocessor 1, the selecting section 72 is set to select the counting section 75, and the interrupt accepting device number Na sent by the counting section 75 is transmitted to the selecting section 72 and the signal line 8. Further, an interrupt acceptance signal A is sent to the signal line 9.

Each peripheral device f2 checks the interrupt acceptance device number Na transmitted via the signal line 8 with its own device number Ns, and receives the interrupt acceptance signal A transmitted via the signal line 9. This confirms that the interrupt requested by the peripheral device 2 whose own device number N3 matches the interrupt accepting device number Na has been accepted.

Further, the microprocessor 1, which has received the interrupt request signal Q# and the interrupt acceptance device number Na, receives the interrupt acceptance device number Na.
It is identified that an interrupt request has been generated from the peripheral device 2 indicated by.

Thereafter, the microprocessor 1 and the peripheral device 2 that received the interrupt transmit and receive required information via the signal line 6.

As is clear from the above description, according to this embodiment, the interrupt control device 7 allocates a time domain in which the interrupt request signal Q can be sent to each peripheral device 2, and receives the interrupt request signal Q. Then, the requesting peripheral device 2 can be immediately identified, and the occurrence of the interrupt request and the requesting peripheral device 2 can be identified by the microprocessor 1.
to notify.

Therefore, the time required to accept an interrupt is shortened, and the load required for interrupt processing on the microprocessor 1 is significantly reduced.

Note that FIG. 2 shows only one embodiment of the present invention, and for example, the configuration of the interrupt control means is not limited to the illustrated interrupt control device 7, and the counters 73 and 75 are shared. Although many modifications may be considered to the effect of the present invention, the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, in the system, the time required to accept an interrupt is significantly shortened, and the load associated with interrupt processing on the processing device is also significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an interrupt control method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional interrupt control method. In the figure, 1 is a microprocessor, 2 is a peripheral device,
3.4.5.6.8 and 9 are signal lines, 7 is an interrupt control device, 71 is a control section, 72 is a selection section, 73 and 75 are counter sections, 74 is a register, A is an interrupt acceptance signal, E is the interrupt interval signal, N is the device number, Na is the interrupt acceptance device number, Ne
indicates the interrupt permission device number, and Q indicates the interrupt request signal. A solid month. Submerged bush 0.72 bile rate 1 field

Claims (1)

[Claims] In a system having an interrupt function from a plurality of peripheral devices (2) to a processing device (1), each of the peripheral devices (2)
) is provided with an interrupt control means (7) for cyclically transmitting a device number assigned in advance to each of the peripheral devices (2) at a constant cycle,
Each of the peripheral devices (2) sends an interrupt request signal (Q) to the interrupt control means (7) in the time domain in which the device number assigned to the device itself is transmitted from the interrupt control means (7). The interrupt control means (7), which has received the interrupt request signal (Q), transmits the device number to be transmitted to each peripheral device (2) by transmitting the device number of the peripheral device that sent the interrupt request signal (Q). In addition to fixing the device number, an interrupt request signal (
Q) and a device number (N) of the peripheral device that sent the interrupt request signal.