JPS61244054A - Method for mounting ic package in input circuit - Google Patents
Method for mounting ic package in input circuitInfo
- Publication number
- JPS61244054A JPS61244054A JP8544085A JP8544085A JPS61244054A JP S61244054 A JPS61244054 A JP S61244054A JP 8544085 A JP8544085 A JP 8544085A JP 8544085 A JP8544085 A JP 8544085A JP S61244054 A JPS61244054 A JP S61244054A
- Authority
- JP
- Japan
- Prior art keywords
- package
- pins
- input
- input circuit
- protruding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は入力回路に於けるICパッケージの実装方法に
懸かるものであって、ICパッケージを入力回路に実装
する場合に於いて、ICパッケージに対する外部ノイズ
の影響を極めて小さなものとすることを可能にしたもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting an IC package in an input circuit. This made it possible to minimize the impact of
従来の技術
従来上り本体の両側から、複数のピンを一面側に突出し
たICパッケージは知られているが、この従来公知のI
Cパッケージは、本体の両側から一面側にのみピンを突
出するものであるため、入力回路にICパッケージを実
装する場合に於いて、外部ノイズの影響を受は易いもの
と成っていた。2. Description of the Related Art Conventionally, an IC package is known in which a plurality of pins are protruded from both sides of an upward main body to one side.
Since the C package has pins protruding from both sides of the main body only to one side, it is easily affected by external noise when the IC package is mounted on an input circuit.
例えば差動アンプ等に於いてICパッケージを並列に実
装する場合、並列するICパッケージの入力ピン相互の
間隔を大きく空けると、外部ノイズが、各入力ピンに与
える強さが異なるものとなり、当然のことながら、外部
ノイズの影響も異なるものとなる。増幅器等の入力回路
に於いて、ローノイズ化、ハイインピーダンス化は重要
な性能向上の要請であるが、各ICパッケージの入力ピ
ンに、外部ノイズの影響が異なるものとして与えられる
のは、各ICパッケージの性能を異なるものとするため
、極めて好ましく無いものである。この外部ノイズの影
響を極力小さなものとするためには、並列する入力ピン
を極限まで接近させることが、外部ノイズから受ける影
響を同一にし、好ましいものである、しかしながら、従
来公知のICバッケ−7は、本体の両側から一面側にの
みビンを突出するものであるため、第3図、第4図に示
すごとく、2.3で現わされる入力ピンを対向近接させ
る事は出来ないもので有った。For example, when mounting IC packages in parallel in a differential amplifier, etc., if there is a large gap between the input pins of the parallel IC packages, the strength of external noise applied to each input pin will differ, which is natural. However, the influence of external noise will also be different. Low noise and high impedance are important performance improvements in input circuits such as amplifiers, but external noise affects the input pins of each IC package differently. This is extremely undesirable because it makes the performance different. In order to minimize the influence of this external noise, it is preferable to place the parallel input pins as close as possible to equalize the influence of external noise. Since the bottle protrudes from both sides of the main body only to one side, the input pins shown in 2.3 cannot be placed close to each other as shown in Figures 3 and 4. There was.
発明が解決しようとする問題点
本発明は上述のごと軽問題点を解決しようとするもので
あって、差動アンプ等に於いてICパッケージを並列に
実装する場合、並列するICパフケ−7の入力ビン相互
の間隔を極限まで接近することを可能とし、外部/イX
が各入力ビンに与える強さを近似したものとすることに
より、外部ノイズの影響を近似させ、増幅器等の入力回
路に於いて、ローノイズ化、ハイインピーダンス化等の
重要な性能向上の要請を実現可能にしようとするもので
ある。Problems to be Solved by the Invention The present invention attempts to solve the above-mentioned minor problems, and when mounting IC packages in parallel in a differential amplifier etc., It is possible to bring the input bins as close as possible to each other, and
By approximating the strength that is applied to each input bin, the influence of external noise can be approximated, achieving important performance improvements such as low noise and high impedance in input circuits such as amplifiers. It attempts to make it possible.
間II息を゛解決するための手段
本発明は上述のごとき問題点を解決するため、本体の両
側から一面側にビンを突出した一方ICパッケージと、
本体の両側から他側面にビンを突出した他方ICパッケ
ージとの組み合わせからなり、この一方ICパッケージ
と他方ICパッケージの入力ピンを対向近接して入力回
路中に接続するもので有る。Means for Solving Interval II In order to solve the above-mentioned problems, the present invention provides an IC package with bottles protruding from both sides of the main body to one side;
It consists of a combination of two IC packages with pins protruding from both sides of the main body and the other IC package, and the input pins of the one IC package and the other IC package are connected to each other in the input circuit in close proximity to each other.
作用
本発明は上述のごとく構成したものであるから、第1図
に示すごと(、差動7ンプ等に於いてICパフケークを
並列に実装する場合、並列するICパッケージの入力ビ
ン相互の間隔を極限まで接近することを可能とし、外部
ノイズが各入力ピンに与える強さを近似したものとする
ことにより、外部ノイズの影響を近似させ、増幅器等の
入力回路に於いて、ローノイズ化、ハイインピーダンス
化等の重要な性能向上の要請を実現可能にすることがで
きる。Operation Since the present invention is constructed as described above, when mounting IC puff cakes in parallel in a differential 7-amp, etc., the interval between the input bins of parallel IC packages can be adjusted as shown in FIG. By approximating the strength of external noise on each input pin, the influence of external noise can be approximated, making it possible to achieve low noise and high impedance in input circuits such as amplifiers. This makes it possible to realize important performance improvement requests such as improvements in performance.
実施例
以下本発明の一実施例を、11図、12図に於いて説明
すれば、本体(1)の両側から一面(2)側に、・複数
のビン(3)を突出した一方ICパフケージ(4,)と
、本体(1)の両側から他面(5)側に複数のビン(3
)を突出した他方ICパフケージ(6)との組み合わせ
から構成されでいる。一方ICパッケージ(4)と、他
方ICパッケージ(6)とは、このように構成すること
により、第1図に示すごとく並列したばあいに、ビン(
3)の配置を全く同一に並べる事が可能となり、この一
方ICパツケーノ(4)と、他方ICパッケー!/(6
)の入力ピン2.3を、対向近接して入力回路中に接a
する事により、入力ピン2.3の相互を限界まで、近接
しで実装することが可能となり、外部ノイズの影響を、
等しく受けるものとなり、結果的に外部ノイズの影響が
無いのと同様の、効果をもたらす事ができる。またこの
一方ICパッケージ(4)と、他方ICパッケージ(6
)は、本体(1)の両側にビン(3)を突出するもので
あれば、特にその種類を問うものではなく、デフタルI
Cパッケージであっても、デエフルインラインパッケー
ジで有っても、また他のもので有っても良い。Embodiment Below, an embodiment of the present invention will be described with reference to FIGS. 11 and 12. One IC puff cage has a plurality of bottles (3) protruding from both sides of the main body (1) to one side (2). (4,), and a plurality of bottles (3) from both sides of the main body (1) to the other side (5).
) in combination with the other IC puff cage (6) which protrudes. By configuring the IC package (4) on the one hand and the IC package (6) on the other hand in this way, when they are arranged in parallel as shown in FIG.
3) can be arranged in exactly the same way, with one IC package (4) and the other IC package! /(6
) input pins 2.3 of
By doing so, it is possible to mount input pins 2 and 3 as close as possible to each other, reducing the influence of external noise.
As a result, it is possible to produce an effect similar to that without the influence of external noise. Also, one IC package (4) and the other IC package (6)
) is not particularly concerned with the type as long as the bottle (3) protrudes from both sides of the main body (1).
It may be a C package, a full inline package, or something else.
発明の効果
★塁[IEII+1−:索消−シl嬬古!たLので本ス
知ム差動アンプ等に於いてICパッケージを並列に実装
する場合、並列するICパッケージの入力ビン相互の間
隔を極限まで接近することを可能とし、外部ノイズが各
入力ピンに与える強さを近似したものとすることにより
、外部ノイズの影響を近似させ、増幅器等の入力回路に
於いて、ローノイズ化、ハイインピーダンス化等の重要
な性能向上のl!晴を実現可能にすることができる。こ
のような性能向上はアナログ回路に於いては勿論、デジ
タル回路に於いても可能であって、作動が高速に成れば
成るほど、入力ピンに対する、外部ノイズの影響が大き
なものと成るから、並列する入力ピンに対する外部ノイ
ズの影響を等しいものとする必要が生じ、この点に於い
て本発明は有効なものである。また本発明に於いては、
ICパッケージを並列に実装するものであるから、回路
の電圧降下等も並列するICパッケージに於いて等しい
ものとなり、回路構成上、有利なものである。Effect of the invention ★ Base [IEII+1-: Search cancellation-Sil Tsumago! Therefore, when mounting IC packages in parallel in a differential amplifier, etc., this system allows the input bins of the parallel IC packages to be placed as close as possible to each other, thereby preventing external noise from reaching each input pin. By approximating the applied strength, the influence of external noise can be approximated, resulting in important performance improvements such as low noise and high impedance in input circuits such as amplifiers! It can make sunny weather possible. This kind of performance improvement is possible not only in analog circuits but also in digital circuits, and the faster the operation, the greater the influence of external noise on the input pins. It becomes necessary to equalize the influence of external noise on parallel input pins, and the present invention is effective in this respect. Further, in the present invention,
Since the IC packages are mounted in parallel, the voltage drop in the circuit is the same for the parallel IC packages, which is advantageous in terms of circuit configuration.
第1図は本発明の一実施例を示すもので、一方ICパッ
ケージと他方ICパッケージの並列状態の平面図、第2
図は一方ICパッケージと他方ICパッケージの斜視図
、tA3図、第4図は従来公知のICパッケージの、異
なる配置例を示す平面図である。
(1)・・・本 体 (2)・・・・・・・・−面(3
)・・・ビ ン (4)・・一方ICパッケーノ(5)
・・・他 面 (6)・・他方ICパッケージ第3図
第4図
第2図
へFIG. 1 shows one embodiment of the present invention, which is a plan view of one IC package and the other IC package in a parallel state;
The figure is a perspective view of one IC package and the other IC package, and Figure tA3 and Figure 4 are plan views showing different arrangement examples of conventionally known IC packages. (1)...Body (2)......-side (3
)...Bin (4)...Meanwhile IC Paccheno (5)
...Other side (6)...Other side IC package Figure 3
Go to Figure 4 Figure 2
Claims (1)
ケージと、本体の両側から他側面にピンを突出した他方
ICパッケージとの組み合わせからなり、この一方IC
パッケージと他方ICパッケージの入力ピンを対向近接
して入力回路中に接続するもので有ることを特徴とする
入力回路に於けるICパッケージの実装方法。It consists of a combination of one IC package with pins protruding from both sides of the main body to one side and the other IC package with pins protruding from both sides of the main body to the other side.
A method for mounting an IC package in an input circuit, characterized in that the input pins of the package and the other IC package are connected in close proximity to each other in an input circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8544085A JPS61244054A (en) | 1985-04-23 | 1985-04-23 | Method for mounting ic package in input circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8544085A JPS61244054A (en) | 1985-04-23 | 1985-04-23 | Method for mounting ic package in input circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61244054A true JPS61244054A (en) | 1986-10-30 |
Family
ID=13858921
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8544085A Pending JPS61244054A (en) | 1985-04-23 | 1985-04-23 | Method for mounting ic package in input circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61244054A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144155A (en) * | 1983-02-08 | 1984-08-18 | Nec Corp | Integrated circuit package |
-
1985
- 1985-04-23 JP JP8544085A patent/JPS61244054A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144155A (en) * | 1983-02-08 | 1984-08-18 | Nec Corp | Integrated circuit package |
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