JPS61241948A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61241948A JPS61241948A JP60083133A JP8313385A JPS61241948A JP S61241948 A JPS61241948 A JP S61241948A JP 60083133 A JP60083133 A JP 60083133A JP 8313385 A JP8313385 A JP 8313385A JP S61241948 A JPS61241948 A JP S61241948A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resin
- semiconductor device
- stress
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止した半導体素子に加わる応力を緩
和するようにする半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device that relieves stress applied to a resin-sealed semiconductor element.
第４図は従来の半導体装置を示す断面図であシ、図にお
いて、（１）は樹脂封止形半導体装置で一般に用いられ
ているリードフレームのダイパッド、（２）はそのリー
ド部、（３）は半導体素子、（４）は半導体素子（３）
の回路を外部と接続するためのボンディングＣ２）
パッド、（５）はリード（２）とポンディングパッド（
４）とを接続するポンディングワイヤー、（６）は素子
表面ｆｆｌ護膜であるパッシベーション膜、（７）ハバ
ッ７７コート膜、（３）は封止樹脂である。FIG. 4 is a sectional view showing a conventional semiconductor device. In the figure, (1) is a die pad of a lead frame commonly used in resin-sealed semiconductor devices, (2) is its lead portion, and (3) is a die pad of a lead frame commonly used in resin-sealed semiconductor devices. ) is a semiconductor element, (4) is a semiconductor element (3)
The bonding pad (C2) for connecting the circuit to the outside, (5) is connected to the lead (2) and the bonding pad (
4) is a bonding wire that connects the two, (6) is a passivation film which is an element surface ffl protective film, (7) is a Hubba 77 coating film, and (3) is a sealing resin.
次に、この半導体装置の製造方法について説明する。ま
ず、シリコーンウェハーに種々の工程を経て作製した回
路は最終的に半導体素子表面保護膜（６）として、リン
ケイ酸ガラス（ＰＥＩＧ ）や窒化シリコン（Ｓｚ３Ｎ
４）等の無機質膜を化学的気相成長（ＣＶＤ）法等によ
り被着される。半導体素子（３）の面積の小さいＩＣで
は問題にはされていなかったが、２５６キロビツト（ｋ
ｂｉｔ） ＤＲＡＭ ｈ！？のように、高集積ＩＣ（Ｖ
Ｉ’３工）では素子面積が大きいので、樹脂封止形半導
体では封止樹脂（８）の残留応力で素子（３）の表面に
応力が発生し、Ａｔ配線のスライド、素子（３）または
樹脂（３）のクラック発生があった０このような不具合
を防止するために、パッシベーションＩＩ （６）の上
に、有機材料、たとえばポリイミドやシリコーン樹脂を
塗布し、熱硬化の後、ダイシングによシウエハーカット
を行い、半導体素子（３）ヲリードフレームのダイパッ
ド（１）に、たとえばＡ＊−８ｉ共晶で接合し、ポンデ
ィングパッド（４）とリード（２）をボンディングワイ
ヤ（５）で接合後、エポキシ樹脂等の熱硬化性樹脂（３
）でモールド成型する方法がとられていた。Next, a method for manufacturing this semiconductor device will be explained. First, the circuit fabricated on a silicon wafer through various processes is finally made of phosphosilicate glass (PEIG) or silicon nitride (Sz3N) as a semiconductor element surface protective film (6).
An inorganic film such as 4) is deposited by chemical vapor deposition (CVD) or the like. This has not been a problem with ICs where the semiconductor device (3) has a small area, but
bit) DRAM h! ? Highly integrated IC (V
Since the element area is large in resin-sealed semiconductors, stress is generated on the surface of the element (3) due to the residual stress of the sealing resin (8), causing the At wiring to slide, the element (3) or Cracks occurred in the resin (3).0 To prevent such problems, an organic material such as polyimide or silicone resin is coated on top of the passivation II (6), and after heat curing, it is diced. Cut the wafer, bond the semiconductor element (3) to the die pad (1) of the lead frame using, for example, A*-8i eutectic, and connect the bonding pad (4) and leads (2) with bonding wire (5). After bonding, thermosetting resin such as epoxy resin (3
) was used.
従来の半導体装置の製造方法では、以上のように、バッ
ファコート膜（７）をスピンコードまたはスクリーン印
刷の後、熱を加えて硬化する必要があり、製造プロセス
が煩雑であるなどの問題点があった０
この発明は上記のような問題点を解消するためになされ
たもので、素子表面に加わる応力を緩和できるとともに
、製造プロセスが簡単で安価な高信頼性の半導体装置が
実現できる製造方法を得ることを目的とする。As described above, in the conventional manufacturing method of semiconductor devices, it is necessary to apply heat to harden the buffer coat film (7) after spin-coding or screen printing, which causes problems such as a complicated manufacturing process. This invention was made to solve the above-mentioned problems, and provides a manufacturing method that can alleviate the stress applied to the element surface, and that can realize a highly reliable semiconductor device with a simple manufacturing process and low cost. The purpose is to obtain.
ｃ問題点を解決するための手段〕
この発明に係、る半導体装置の製造方法は、バッフアコ
−）Ｍトｔ、て、パッシベーション膜上に製造プロセス
が簡単なＡ、ｔ＠ｔ−被着することにより樹脂封止によ
り加わる素子表面の応力をＡｔ膜で緩和するようにした
ものである。Means for Solving Problem C] The method for manufacturing a semiconductor device according to the present invention is to deposit A, t@t, which has a simple manufacturing process, on a passivation film. This allows the At film to relieve stress on the element surface that is applied due to resin sealing.
この発明におけるバッファコート膜はＡｔの性質である
塑性変形性を利用することによシ、樹脂の熱収縮による
残留応力を素子表面に極力加わらないようにする。The buffer coat film in this invention utilizes the plastic deformability which is a property of At to minimize the application of residual stress due to thermal contraction of the resin to the element surface.
第１図はこの発明の一実施例の方法で製造された半導体
装置の断面図で、第１図において、第４図の従来例と同
一符号は同等部分を示し、説明の恵複を避ける。そして
、（９）はＡｔ膜でパッシベーション膜（６）の上に蒸
着されている。FIG. 1 is a sectional view of a semiconductor device manufactured by a method according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in the conventional example of FIG. 4 indicate equivalent parts to avoid redundant explanation. Further, (9) is an At film deposited on the passivation film (6).
このように構成された半導体装置において、実際に半導
体素子表面に働く応力がバッファコート膜がない場合と
比べ減少していることを光弾性の手法を用いて確認した
。以下、その結果について述べる。第２図（ａ）および
（ｂ）はそれぞれ、バッファコート膜が無い構造の場合
、およびとの実施例製造方法で得られる構造の場合の樹
脂封止後の応力分布を光弾性の手法で計測した結果であ
る。試料は第４因および第１図に示したような半導体装
置の断面を約Ｉｎｍの厚さにスライスしたものである。In the semiconductor device configured in this way, it was confirmed using a photoelastic technique that the stress actually acting on the surface of the semiconductor element was reduced compared to the case without the buffer coat film. The results will be described below. Figures 2 (a) and (b) show the stress distribution after resin sealing measured using a photoelastic method for a structure without a buffer coat film and a structure obtained by the manufacturing method of the example. This is the result. The sample was obtained by slicing the cross section of the semiconductor device shown in the fourth factor and FIG. 1 to a thickness of about Inm.
第２図の線σＱは半導体素子周辺に現われた光弾性によ
る縞模様を示し、各々の線上では主応力差が一定でおる
ことを示す。縞数が多い程応力が集中していることを示
すので、この実施例による場合素子表面に加わる応力が
緩和されていることが分かる。この様子をさらに明確に
した結果を第３図に示す。これは光弾性計測から得られ
たデータをさらに解析し、半導体素子表面に働く応力成
分を水平方向に働くせん断応力（τ）と圭直に働く応力
（σ：引張夛ヲ正、圧縮を負）を求めた結果である。The line σQ in FIG. 2 shows a photoelastic striped pattern appearing around the semiconductor element, and shows that the principal stress difference remains constant on each line. Since the greater the number of stripes, the more concentrated the stress, it can be seen that the stress applied to the element surface is relaxed in this example. Figure 3 shows the results that further clarify this situation. This is based on further analysis of the data obtained from photoelastic measurements, and the stress components acting on the surface of the semiconductor element are divided into horizontal shear stress (τ) and direct stress (σ: positive for tension, negative for compression). This is the result of finding.
図において、横軸は半導体素子のエツジからの距離Ｘ（
任意単位）、縦軸は半導体素子（３）の表面での樹脂（
８）に加わる応力（任意単位）である。実線で描いた曲
線αηおよび（６）はそれぞれバッファコート（９）が
無い場合のせん断応力および垂直応力を示し、破線で描
いた曲線（至）およびＱ４）はそれぞれこの実施例によ
る構造の場合に得られたせん断応力および垂直応力曲線
を示す。応力の分布の傾向は両者において共通している
が、その絶対値はこの実施例による構造の場合の方が明
らかに低減しており、本発明の製造方法によって得られ
る構造の応力緩和効果を証明している。In the figure, the horizontal axis is the distance X(
The vertical axis is the resin (arbitrary unit) on the surface of the semiconductor element (3).
8) is the stress (in arbitrary units) applied to The curves αη and (6) drawn in solid lines show the shear stress and normal stress, respectively, in the absence of buffer coat (9), and the curves (to) and Q4) drawn in dashed lines, respectively, in the case of the structure according to this example. The obtained shear stress and normal stress curves are shown. Although the tendency of stress distribution is common in both cases, its absolute value is clearly lower in the structure according to this example, proving the stress relaxation effect of the structure obtained by the manufacturing method of the present invention. are doing.
なお、上記実施例ではＡｔ膜（９）はフローティング状
態になっているが、このＡｔ膜（９）と素子（３）のグ
ランド回路と接続しておけば、Ａｔ膜（９）の電位は零
となるので、樹脂（８）の透湿による水との電池作用が
軽減され、素子（３）のＡｔ配線腐食の問題も低減する
ばかりではなく、樹脂（３）に静電帯電したチーヤージ
をＡｔ膜（９）を通しアースされ、静電破壊に対しても
強い半導体装置が得られる。In the above example, the At film (9) is in a floating state, but if this At film (9) is connected to the ground circuit of the element (3), the potential of the At film (9) becomes zero. Therefore, the battery effect with water due to the moisture permeation of the resin (8) is reduced, and the problem of At wiring corrosion of the element (3) is also reduced, as well as the electrostatically charged charge on the resin (3) is removed by At. A semiconductor device that is grounded through the film (9) and is resistant to electrostatic damage can be obtained.
また、Ａｔ膜（９）は蒸着以外にスパッタリング、また
は、化学的気相成長法で形成してもよい。Furthermore, the At film (9) may be formed by sputtering or chemical vapor deposition instead of vapor deposition.
以上のように、この発明によればバッファコート膜とし
て、Ａｔを被着させるようにしたので、安。As described above, according to the present invention, since At is deposited as the buffer coat film, it is inexpensive.
価で、信頼性の高い半導体装置が製造できる効果がある
。This has the effect of making it possible to manufacture semiconductor devices with low cost and high reliability.
４１図はこの発明の一実施例方法で製造された半導体装
置の断面図、５ｇ２図は本発明の詳細な説明するための
光弾性による応力線図、第３図は本発明の詳細な説明す
るための半導体素子近傍の応力分布図、第４図は従来の
半導体装置の一例を示す断面図である。
因において、（３）は半導体素子、（６）はパッシベー
ション膜、（８）は封止樹脂、（９）はバッファコート
膜としてのＡｔ膜である。
なお、図中同一符号は同−又は相当部分を示す。Figure 41 is a cross-sectional view of a semiconductor device manufactured by a method according to an embodiment of the present invention, Figure 5g2 is a stress diagram due to photoelasticity for explaining in detail the present invention, and Figure 3 is a diagram for explaining in detail the present invention. FIG. 4 is a cross-sectional view showing an example of a conventional semiconductor device. In the above, (3) is a semiconductor element, (6) is a passivation film, (8) is a sealing resin, and (9) is an At film as a buffer coat film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (4)
膜の上にアルミニウム膜を形成した後に全体を樹脂封止
することを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, which comprises forming an aluminum film on a passivation film formed on the top surface of a semiconductor device, and then sealing the entire semiconductor device with a resin.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the aluminum film is formed by a vacuum evaporation method.
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the aluminum film is formed by a sputtering method.
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the aluminum film is formed by chemical vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083133A JPS61241948A (en) | 1985-04-18 | 1985-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083133A JPS61241948A (en) | 1985-04-18 | 1985-04-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61241948A true JPS61241948A (en) | 1986-10-28 |
Family
ID=13793699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60083133A Pending JPS61241948A (en) | 1985-04-18 | 1985-04-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61241948A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
-
1985
- 1985-04-18 JP JP60083133A patent/JPS61241948A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5613295A (en) * | 1990-12-20 | 1997-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US5646830A (en) * | 1990-12-20 | 1997-07-08 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
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