JPS61240665A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61240665A JPS61240665A JP8182785A JP8182785A JPS61240665A JP S61240665 A JPS61240665 A JP S61240665A JP 8182785 A JP8182785 A JP 8182785A JP 8182785 A JP8182785 A JP 8182785A JP S61240665 A JPS61240665 A JP S61240665A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- thermal expansion
- copper
- semiconductor element
- expansion coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置、特にパワー半導体素子を組み込ん
だ半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices, particularly semiconductor devices incorporating power semiconductor elements.
（ロ）従来の技術
従来の半導体装置は第２図に示す如く、アルミ基板（ト
）上の導電路上に銅で形成したヒートシンク（ロ）を介
してシリコンパワー半導体素子＠を固着していた。上述
した技術によると銅の熱膨張率が１６．７ Ｘ １０７
℃、シリコンの熱膨張率が２．４×１０”／’Ｃとなる
為両者の熱膨張率が著しく異なり温度サイクルによって
半導体素子（イ）を固着するろう材にクラックが発生す
る欠点があった。他の従来例として銅とシリコンの熱膨
張率を緩和する為に第３図に示す如く、アルミ基板００
上に銅のヒートシンク（ロ）およびシリコンと熱膨張率
のほぼ等しいモリブデン板（至）を介してシリコンパワ
ー半導体素子（２）を固着することによりクラックの発
生を防止していた。(B) Prior Art As shown in FIG. 2, in a conventional semiconductor device, a silicon power semiconductor element is fixed on a conductive path on an aluminum substrate (G) via a heat sink (B) formed of copper. According to the above technology, the coefficient of thermal expansion of copper is 16.7 x 107
℃, the coefficient of thermal expansion of silicon is 2.4 x 10''/'C, so the coefficient of thermal expansion of the two is significantly different, and there is a drawback that cracks occur in the brazing material that fixes the semiconductor element (a) due to temperature cycles. .As another conventional example, in order to reduce the coefficient of thermal expansion of copper and silicon, as shown in Fig. 3, an aluminum substrate 00
The occurrence of cracks was prevented by fixing the silicon power semiconductor element (2) thereon via a copper heat sink (b) and a molybdenum plate (t) having a coefficient of thermal expansion substantially equal to that of silicon.
斯る従来技術として例えば特開昭５１−６６７２号公報
等が知られる。As such a conventional technique, for example, Japanese Patent Laid-Open No. 51-6672 is known.
（ハ） 発明が解決しようとする問題点上述した従来の
構造ではクラックの発生は低減できるが、モリブデン板
が高価である為コスト高になる欠点がある。またモリブ
デン板の介在により半導体素子からアルミ基板までの熱
抵抗が増加する欠点もある。更にモリブデン板を使用し
ない場合は半導体素子を固着するろう材にクラックが発
生する欠点があった。(c) Problems to be Solved by the Invention Although the conventional structure described above can reduce the occurrence of cracks, it has the disadvantage of increasing costs because the molybdenum plates are expensive. Another drawback is that the presence of the molybdenum plate increases the thermal resistance from the semiconductor element to the aluminum substrate. Furthermore, when a molybdenum plate is not used, there is a drawback that cracks occur in the brazing material that fixes the semiconductor element.
に）問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであり、第１
図に示す如く金属基板（１）上に銅（４）、インバー（
５） 、銅（４）の３層に積層したヒートシンク（２）
を使用し、その上面に半導体素子（３）を固着するもの
である。B) Means for Solving the Problems The present invention has been made in view of the above points, and
As shown in the figure, copper (4) and invar (
5) Heat sink (2) laminated with three layers of copper (4)
A semiconductor element (3) is fixed on the upper surface of the semiconductor element.
（ホ）作用
本発明に依ればヒートシンクを３層に積層することによ
りヒートシンクの熱膨張率と半導体素子の熱膨張率とを
緩和することができる。(E) Function According to the present invention, by stacking the heat sink in three layers, the coefficient of thermal expansion of the heat sink and the coefficient of thermal expansion of the semiconductor element can be reduced.
（へ）実施例
本発明に依る半導体装置は第１図に示す如く、金属基板
（１）上に３層に積層したヒートシンク（２）を介して
パワー半導体素子（３）を固着するものである。(F) Embodiment As shown in FIG. 1, the semiconductor device according to the present invention is one in which a power semiconductor element (3) is fixed on a metal substrate (1) via a heat sink (2) laminated in three layers. .
金属基板（１）は良熱伝導性のアルミニウムで形成され
その表面は酸化アルミニウム膜で被覆してもよい。The metal substrate (1) is made of aluminum having good thermal conductivity, and its surface may be coated with an aluminum oxide film.
ヒートシンク（２）は銅（４）、インバー（５）、銅（
４）の夫ローラーでクラッドし圧延工程で所定の厚にな
るまで伸し、プレスで所定の大きさに打抜き、半導体素
子（３）を固着できる様に銀又はニッケル等でメッキを
行なう。The heat sink (2) is made of copper (4), invar (5), copper (
4) It is clad with a husband roller, stretched to a predetermined thickness in a rolling process, punched into a predetermined size with a press, and plated with silver or nickel so that the semiconductor element (3) can be fixed.
インバー（５）はニッケル３６％、鉄６４％の合金であ
る。インバー（５）の熱膨張率は１． ｓ Ｘ １ ｏ
−’／℃に対しモリブデンの熱膨張率は５．５ Ｘ １
０−’／’Ｃであり、インバー（５）はモリブデンの約
１／３の熱膨張率である。熱膨張率はモリブデンより好
結果を得られる。Invar (5) is an alloy of 36% nickel and 64% iron. The thermal expansion coefficient of Invar (5) is 1. s X 1 o
-'/°C, the thermal expansion coefficient of molybdenum is 5.5 x 1
0-'/'C, and Invar (5) has a coefficient of thermal expansion that is about 1/3 that of molybdenum. Better thermal expansion coefficient than molybdenum can be obtained.
前記ヒートシンク（２）上に半導体素子（３）をろう付
し、次に金属基板（１）上にヒートシンク（２）をろう
付する。A semiconductor element (3) is brazed onto the heat sink (2), and then the heat sink (2) is brazed onto the metal substrate (1).
斯る本発明の構造に依ればヒートシンク（２）の３層の
積層の割合を１対１対１にすることに依り熱膨張率が１
１×１０／°Ｃとなり銅（４）の熱膨張率より小さくな
る。又前記積層の割合を１対３対１にすれば熱膨張率は
６ Ｘ １０−’／℃となりシリコンの熱膨張率に近く
なる。According to the structure of the present invention, the coefficient of thermal expansion can be reduced to 1 by setting the ratio of the three layers of the heat sink (2) to 1:1:1.
The coefficient of thermal expansion is 1×10/°C, which is smaller than that of copper (4). If the ratio of the laminated layers is 1:3:1, the coefficient of thermal expansion will be 6 x 10-'/°C, which is close to the coefficient of thermal expansion of silicon.
（ト）発明の効果
本発明に依ればヒートシンクを銅、インバー、銅の３層
に積層することによりシリコンパワー半導体素子を固着
するろう材の劣化を防止でき且つモリブデン板を使用す
る場合よりも熱伝導度がよくなり放熱性に優れる。又、
本発明に依るヒートシンクは銅、インバー等の安価な材
料ででき、極めて量産に適するヒートシンクを実現でき
る。(G) Effects of the Invention According to the present invention, by laminating the heat sink in three layers of copper, invar, and copper, it is possible to prevent deterioration of the brazing filler metal that fixes the silicon power semiconductor element, and it is better than the case where a molybdenum plate is used. Good thermal conductivity and excellent heat dissipation. or,
The heat sink according to the present invention is made of inexpensive materials such as copper and invar, and can realize a heat sink that is extremely suitable for mass production.
第１図は本発明による実施例を示す断面図、第２図およ
び第３図は従来例を示す断面図である。
（１）・・・金属基板、（２）・・・ヒートシンク、（
３）・・・半導体素子、（４）・・・銅、（５）−・・
インバー。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 靜 夫
第２図
第３図FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a conventional example. (1)...Metal substrate, (2)...Heat sink, (
3)...Semiconductor element, (4)...Copper, (5)-...
Invar. Applicant: Sanyo Electric Co., Ltd., and 1 other representative: Patent attorney: Yasuo Sano Figure 2 Figure 3
Claims (1)
パワー半導体素子を固着する半導体装置に於いて、前記
ヒートシンクは両主面を銅板で形成し、該銅板間に熱膨
張係数の低い金属を挿入し、前記パワー半導体素子との
熱膨張係数の差を縮少させることを特徴とする半導体装
置。 ２、特許請求の範囲第１項に於いて、前記熱膨張係数の
低い金属としてインバーを用いることを特徴とした半導
体装置。[Claims] 1. In a semiconductor device in which a power semiconductor element is fixed on a metal substrate via a heat sink with good thermal conductivity, both main surfaces of the heat sink are formed of copper plates, and heat is distributed between the copper plates. A semiconductor device characterized in that a metal having a low expansion coefficient is inserted to reduce a difference in thermal expansion coefficient between the power semiconductor element and the power semiconductor element. 2. A semiconductor device according to claim 1, wherein invar is used as the metal having a low coefficient of thermal expansion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8182785A JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8182785A JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61240665A true JPS61240665A (en) | 1986-10-25 |
| JPH0322706B2 JPH0322706B2 (en) | 1991-03-27 |
Family
ID=13757304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8182785A Granted JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61240665A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02104641U (en) * | 1989-02-06 | 1990-08-20 | ||
| JPH0475369A (en) * | 1990-07-18 | 1992-03-10 | Hitachi Ltd | Electronic device and engine ignition device using the same |
| JPH0511450U (en) * | 1991-07-22 | 1993-02-12 | 三洋電機株式会社 | Hybrid integrated circuit |
| JPH0515440U (en) * | 1991-07-31 | 1993-02-26 | 京セラ株式会社 | Package for storing optical semiconductor devices |
| JPH06188324A (en) * | 1992-12-16 | 1994-07-08 | Kyocera Corp | Semiconductor device |
| EP0746022A1 (en) * | 1995-05-30 | 1996-12-04 | Motorola, Inc. | Hybrid multi-chip module and method of fabricating |
| GB2401481A (en) * | 2003-04-30 | 2004-11-10 | Agilent Technologies Inc | Application specific heat sink assembly |
| JP2006013368A (en) * | 2004-06-29 | 2006-01-12 | Sanyo Electric Co Ltd | Circuit device and manufacturing method thereof |
| US7456492B2 (en) | 2005-12-26 | 2008-11-25 | Denso Corporation | Semiconductor device having semiconductor element, insulation substrate and metal electrode |
-
1985
- 1985-04-17 JP JP8182785A patent/JPS61240665A/en active Granted
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02104641U (en) * | 1989-02-06 | 1990-08-20 | ||
| JPH0475369A (en) * | 1990-07-18 | 1992-03-10 | Hitachi Ltd | Electronic device and engine ignition device using the same |
| JPH0511450U (en) * | 1991-07-22 | 1993-02-12 | 三洋電機株式会社 | Hybrid integrated circuit |
| JPH0515440U (en) * | 1991-07-31 | 1993-02-26 | 京セラ株式会社 | Package for storing optical semiconductor devices |
| JPH06188324A (en) * | 1992-12-16 | 1994-07-08 | Kyocera Corp | Semiconductor device |
| EP0746022A1 (en) * | 1995-05-30 | 1996-12-04 | Motorola, Inc. | Hybrid multi-chip module and method of fabricating |
| US5751552A (en) * | 1995-05-30 | 1998-05-12 | Motorola, Inc. | Semiconductor device balancing thermal expansion coefficient mismatch |
| GB2401481A (en) * | 2003-04-30 | 2004-11-10 | Agilent Technologies Inc | Application specific heat sink assembly |
| GB2401481B (en) * | 2003-04-30 | 2006-07-12 | Agilent Technologies Inc | Heat sink |
| JP2006013368A (en) * | 2004-06-29 | 2006-01-12 | Sanyo Electric Co Ltd | Circuit device and manufacturing method thereof |
| US7456492B2 (en) | 2005-12-26 | 2008-11-25 | Denso Corporation | Semiconductor device having semiconductor element, insulation substrate and metal electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0322706B2 (en) | 1991-03-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |