JPS61230196A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Background of the Invention ■ This invention provides a display control device for a display device configured by arranging display pixels such as LEDs in a matrix.
io.

(B) Background of the Invention The display device configured as described above displays image data by driving and controlling the column drive circuit that drives and controls the columns of the matrix and the row drive circuit that drives and controls the rows of the matrix.
Image data (character code) displayed on this display device is generally stored in one RAM.

Therefore, when displaying the image data (character code) stored in this RAM, the image data (character code) corresponding to the amount of display at one time is read out from this RAM, and the dot pattern data for displaying the image data (character code) is read out from this RAM.
In other words, it converts to dot data, controls the display of this dot data, and when this display ends, reads the image data (character code) for the next display from RAM and converts it again to dot data. I was doing the same thing over and over again.

In this way, each time the display control ends, the image data is read out,
Performing the conversion operation takes a long time, which poses a problem in that high-speed display tlIJtll is not possible.

(c) Purpose of the Invention This invention uses two RAMs, one of which stores display image data, and the other one of which stores display control dot data. It is an object of the present invention to provide a display control device that can shorten processing time for reading and converting data.

(D) Summary of the Invention The present invention comprises a first storage means for storing image data for display, a second storage means for storing dot data for display corresponding to the display amount of - times, Display control is performed on the display device using the dot data stored in the second storage means, and during this display control, image data to be displayed next is read from the first storage means and converted into dot data for display. The present invention is characterized in that the display control device includes a control means for controlling the display.

(E) Effects of the Invention According to this invention, one of the two storage means stores image data for display, and the other stores dot data for display control by the display device, so that the other While dot data is being read and displayed from one storage means, editing processing such as reading image data to be displayed next from one storage means and converting it into dot data can be performed, thereby reducing data processing time.

Further, since the dot data is stored in an independent storage means, the data can be read out freely, and the display can be easily controlled to freeze or scroll the displayed image.

(f) Examples of the invention An embodiment of the present invention will be described in detail below based on the drawings.

The drawing shows a display control device that controls the display of a display device configured by arranging LEDs in a matrix, and in the drawing, display @ 10 is a display 12 formed by arranging LEDs 1 in a matrix of 16×192. In this display 12, each anode and each cathode of each LED 11 are connected by vertical and horizontal lines, respectively, each connected cathode land is connected to a cathode driver 13, and each connected anode land is connected to a cathode driver 13. are connected to the anode driver 14, and latch circuits 15... are connected to the anode, and these latch circuits 15... divide the anode land into predetermined groups and designate each of these divided groups.

The CPU 16 drives each circuit device according to the program stored in the 0M17.

The image data displayed on the aforementioned display device 10 is inputted, for example, from a personal computer or the like, and this image data is stored in the character code holding area 19a of the first RAM 19.

In addition to the above-mentioned character code holding area 19a, the first RAM 19 has a display dot data holding area 1.
9b, and in this area 19b, dot data corresponding to one display amount to be displayed on the display device 10 and dot data for preparation for the next display are stored.

In this system, the second RAM 20 is
M20 is for holding display dot data, and is for display device 1.
10 stores the display dot data of the amount displayed at one time. At this time, dot data writing from the CPU 16 can also be performed at the same time.

A first gate 21 and a second gate 22 are connected to the second RAM 20, and these gates 21 and 22 are connected to the CPL.
Gate control is performed by a latch circuit 23 controlled by J16.

The data bus of the CPU 16 is connected to the first gate circuit 21 described above, and from this gate 21 each latch circuit 15.
..., and this gate 21 transfers the dot data from the CPU 16 to the second RAM 20 and each latch circuit 15...
・With this control, the second RAM 20 is switched to:
It becomes possible to write and read dot data.

The aforementioned second gate 22 is connected to an address bus corresponding to the aforementioned data bus from the CPU 16 and the aforementioned latch circuit 2.
The cathode drive signal of No. 3 and the latch drive signal from the counter 24 are connected, and this second gate 22 switches and controls the address bus and both drive signals for the second RAM 20, and this! By performing the 1 control in synchronization with the control of the first gate 21 described above, dot data is loaded into and read out from the second RAM 20.

That is, the data bus and address bus are connected to the gate 11.
When all is inputted into the second RAM 20, the dot data is stored in the area specified by the address data. At this time, dot data is also stored in the display dot data holding area 19b at the same time.

Further, the cathode drive signal output from the latch circuit 23 is a signal for driving the cathode driver 13, and this signal includes an address specifying each cathode land, and the count value of the counter 24 is Latch circuit 1
This signal drives the latch circuits 15, 15, . . ., and includes an address specifying each latch circuit 15, .

As a result, by inputting both drive signals to the second RAM 20, the address of the dot data stored in the second RAM 20 is designated, and the dot data is read out.

The aforementioned counter 24 is now in the CPU 16! lJt[l, and counts the pulses output from the clock pulse generation circuit 25 and outputs the counted value (drive signal).The decoder 26 decodes the signal of the counted value and converts the decoded signal (
latch enable signal) is output to the latch circuits 15 .

Further, the cathode drive signal output from the latch circuit 23 is decoded by the decoder 27, and the decoded signal (scan signal) is output to the cathode driver 13.

The display 1tIIJ all device configured in this way is c
When image data is input to the PU i6, this image data (consisting of character codes) is sequentially stored in the character code holding area 19a of the first RAM 19.

Next, the image data corresponding to the display amount of - times is transferred to the lRA.
M19 character code holding area 19a to CP
The character generator 18 converts the image data 9 into dot pattern data for display, that is, dot data.

Next, the first and second gates 21 and 22 are connected to the write side of the second RAM 20, and the second RAM
20 and the display dot data holding area 19b of the first RAM 19, the dot data and its address are output, and this dot data is stored in the second RAM 20 and the area 19b of the first RAMI 9.

Next, the CPL 116 provides the read side of the second RAM 20 with
Gate-controls the first and second gates 21 and 22, and also controls the latch circuit 23 and counter 24 to
Read the dot data stored in M20.

At the same time, the cathode driver 13 and the anode driver 14
, latch circuit 15... are driven, so the second RAM
The dot data read out from 20 is input to display 12 and displayed.

Note that the CPU 16 has a latch circuit 23 and a counter 24.
By controlling , the display image displayed on the display 12 can be scrolled or frozen.

Further, as described above, while the display of the dot data stored in the second RAM 20 is being controlled, the CPU 16 uses an interrupt process to transfer the amount of image data to be displayed next to the character code holding area 19 of the first RAM 19.
This image data is converted into dot data by the character generator 18, and the process waits.

By repeatedly executing such processing, the display 12
The images are displayed in sequence.

According to this embodiment, by providing the second RAM 20,
The processing time for reading image data to be displayed next and converting dot data is shortened, and the displayed image can be easily scrolled or frozen.

In the above-described embodiments, the display pixels are LED II, but other display pixels such as lamps and fluorescent materials may also be used.

Regarding the correspondence between the structure of the present invention and the structure of the above-described embodiment, the display pixel of the present invention corresponds to the LED 1 of the embodiment, and the display device below corresponds to the display device 10, The storage means corresponds to the first RAM 19, the second storage means corresponds to the second RAM 20, and the control means corresponds to the CP
Corresponding to tJ16, the configuration of the present invention is not limited to the above-described embodiment.

[Brief explanation of drawings]

The drawing shows a display control device 1lJ showing one embodiment of the present invention.
It is a circuit block diagram. 10...Display device 11...LED12...
・Indicator 13...Cathode driver 14...
・Anode driver 15... Ledge circuit 16...
CPtJ 19...1st RAM20...
・Second RAM 21...First gate 22...
2nd gate

Claims (1)

[Scope of Claims] 1. A display device that controls the display of an image by controlling a column drive circuit that drives columns of display pixels arranged in a matrix and a row drive circuit that drives horizontal rows; A first storage means for storing image data, a second storage means for storing dot data corresponding to one display amount, and display control of a display device using the dot data stored in the second storage means. , a display control device comprising: & control means for reading image data to be displayed next from the first storage means during the display control and converting it into dot data for display.