JPS61224355A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61224355A JPS61224355A JP60063425A JP6342585A JPS61224355A JP S61224355 A JPS61224355 A JP S61224355A JP 60063425 A JP60063425 A JP 60063425A JP 6342585 A JP6342585 A JP 6342585A JP S61224355 A JPS61224355 A JP S61224355A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor device
- region
- thickness
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000005360 phosphosilicate glass Substances 0.000 description 16
- 230000005865 ionizing radiation Effects 0.000 description 12
- 230000003321 amplification Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 231100000987 absorbed dose Toxicity 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/40—Vertical BJTs
- H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置及びその製造方法に関し、特にバイ
ポーラトランジスタを有する半導体装置及びその製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a bipolar transistor and a method for manufacturing the same.
第１図は従来の半導体装置の一例を示す断面図である。 FIG. 1 is a sectional view showing an example of a conventional semiconductor device.
この図に示した半導体装置は、デバイスエレクトロニク
ス フォーインテグレーティッドサーキッツアール・ニ
ス・ミューラー及び、ティー・アイ・カミンス（ジョン
ライレイ アンドソンズ）第２３０頁（Ｄｅｖｉｃｅ
Ｅｌｅｃｔｒｏｎｉｃｓ ｆｏｒＩ ｎｔｅｇｒａｔｅ
ｄ Ｃ１ｒｃｕｉｔｓ Ｒ、Ｓ 、 Ｍｕｌｌｅｒ ＆
Ｔ 、 Ｉ 。The semiconductor device shown in this figure was published by Device Electronics Four Integrated Circuits R.N.
Electronics for I integrate
d C1rcuits R, S, Muller &
T, I.
Ｋａｍｉｎｓ （ｊｏｈｎ Ｗｉｌｅｙ ＆ ５ｏｎｓ
） ｐｐ−２３０）にも記載されている。第１図におい
て、１１は高濃度ｎ形シリコン層、１２はｎ形エピタキ
シャル層、１３はシリコン酸化膜、１４は多結晶シリコ
ン層、１５は電極である。Kamins (John Wiley & 5ons
) pp-230). In FIG. 1, 11 is a high concentration n-type silicon layer, 12 is an n-type epitaxial layer, 13 is a silicon oxide film, 14 is a polycrystalline silicon layer, and 15 is an electrode.
また、第２図は従来の別の半導体装置の一例を示す断面
図である。この図に示した半導体装置は、上述の文献第
２８９頁にも記載されている。第２図において、２１は
ｎ形シリコン基板、２２は高濃度ｎ形エピタキシャル層
、２３はｎ形エピタキシャル層、２４は高濃度Ｐ形分離
領域、２５は高濃度Ｐ影領域、２６は高濃度ｎ影領域、
２７はシリコン酸化膜、２８は電極である。Further, FIG. 2 is a sectional view showing an example of another conventional semiconductor device. The semiconductor device shown in this figure is also described on page 289 of the above-mentioned document. In FIG. 2, 21 is an n-type silicon substrate, 22 is a high concentration n-type epitaxial layer, 23 is an n-type epitaxial layer, 24 is a high concentration P-type isolation region, 25 is a high concentration P shadow region, and 26 is a high concentration n shadow area,
27 is a silicon oxide film, and 28 is an electrode.
上記シリコン酸化膜１３．２７は、トランジスタを形成
する以前に、ｎ形エピタキシャル層１２゜２３の表面を
熱酸化法により厚く酸化することにより形成されている
。このような従来の半導体装置に電離性放射線を照射す
ると、トランジスタの電流増幅率の低下が生じることが
問題となっている。The silicon oxide film 13.27 is formed by thickly oxidizing the surface of the n-type epitaxial layer 12.23 by thermal oxidation before forming the transistor. When such a conventional semiconductor device is irradiated with ionizing radiation, a problem arises in that the current amplification factor of the transistor decreases.
本発明の目的は、上記従来の半導体装置の問題点を改善
し、電離性放射線耐量を増した半導体装置を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to improve the problems of the conventional semiconductor device described above and to provide a semiconductor device with increased resistance to ionizing radiation.
前述のごとく、一般にバイポーラトランジスタに電離性
放射線を照射すると、電流増幅率の低下が生じることが
知られている。この原因は、電離性放射線照射により半
導体基板と酸化膜との間に界面準位が形成されると共に
、酸化膜中に正の固定電荷が多く形成、蓄積され、この
界面準位及び正の固定電荷を通して、正孔・電子の再結
合が生じ表面再結合電流が増加することによると考えら
れている。しかし、これらの界面準位及び正の固定電荷
は、酸化膜厚が薄いほど蓄積されにくいため、電離性放
射線耐量を増すために薄い酸化膜を形成することが必要
となる。As mentioned above, it is generally known that when a bipolar transistor is irradiated with ionizing radiation, the current amplification factor decreases. The cause of this is that interface states are formed between the semiconductor substrate and the oxide film due to ionizing radiation irradiation, and many positive fixed charges are formed and accumulated in the oxide film. It is thought that this is due to the recombination of holes and electrons occurring through the charge, increasing the surface recombination current. However, these interface states and positive fixed charges are less likely to accumulate as the oxide film becomes thinner, so it is necessary to form a thin oxide film in order to increase the resistance to ionizing radiation.
しかし、酸化膜厚を単に薄くシチだけでは、製造工程中
で生ずる各種のイオン性電荷等のため、初期特性が著し
く低下したり、低電流域の電流利得が低下したり、また
Ｂ−Ｔ処理等によるドリフトや信頼性の低下を招く。However, if the oxide film thickness is simply made thinner, the initial characteristics will deteriorate significantly due to various ionic charges generated during the manufacturing process, the current gain in the low current range will decrease, and the B-T treatment etc., resulting in drift and reduced reliability.
そこで、本発明では、酸化膜とその上に形成した絶縁膜
の組み合わせにより、薄い酸化膜に対するイオン性電荷
の影響を防止するものである。また、酸化膜形成後、熱
処理、イオン拡散、イオン打込みなど各種の工程を経る
ことによる該酸化膜中及び該酸化膜と基板との間で、結
晶欠陥が生じたり、トラップ準位が増加したりするのを
防止するため、トランジスタ形成後に上記の複合膜すな
わち酸化膜及び絶縁膜を形成することを特徴とする。Therefore, the present invention uses a combination of an oxide film and an insulating film formed thereon to prevent the influence of ionic charges on the thin oxide film. Furthermore, after the oxide film is formed, crystal defects may occur in the oxide film or between the oxide film and the substrate due to various processes such as heat treatment, ion diffusion, and ion implantation, and trap levels may increase. In order to prevent this, the above-mentioned composite film, that is, an oxide film and an insulating film, is formed after the transistor is formed.
以下、本発明の実施例を詳細に説明する。 Examples of the present invention will be described in detail below.
第３図は本発明の半導体装置の実施例を示す断面構造図
である。FIG. 3 is a cross-sectional structural diagram showing an embodiment of the semiconductor device of the present invention.
本実施例の半導体装置は、素子の形成された表面に、膜
厚の薄い、例えば５０〜２００人のシリコン酸化膜３３
を有し、このシリコン酸化膜３３の表面に、膜厚の厚い
例えば５００〜３０００人のリンけい酸ガラス膜（ＰＳ
Ｇ膜）３６が形成されている。The semiconductor device of this embodiment has a thin silicon oxide film 33 of, for example, 50 to 200 layers, on the surface on which the elements are formed.
On the surface of this silicon oxide film 33, a thick phosphosilicate glass film (PS) of, for example, 500 to 3000
G film) 36 is formed.
この複合膜により、電離性放射線照射による固定電荷の
蓄積が減少し、界面の影響が抑えられ。This composite film reduces the accumulation of fixed charges due to ionizing radiation exposure and suppresses the effects of interfaces.
バイポーラトランジスタの電流増幅率の低下を抑えるこ
とができる。具体的にこの効果の一例を示すと、現状の
バイポーラトランジスタに約１×１０５ｒａｄ相当の電
離性放射線を照射したところ、電流増幅率が照射前の５
０％にまで低下していたが、本実施例の半導体装置では
約６Ｘ１０５ｒａｄ相当の電離性放射線を照射して、電
流増幅率が照射前の５０％に低下することが確認され、
放射線耐量の増加が示された。It is possible to suppress a decrease in the current amplification factor of the bipolar transistor. To give a concrete example of this effect, when a current bipolar transistor is irradiated with ionizing radiation equivalent to about 1 x 105 rad, the current amplification factor is 5
However, in the semiconductor device of this example, it was confirmed that the current amplification factor decreased to 50% of the value before irradiation when irradiated with ionizing radiation equivalent to about 6 x 105 rad.
An increase in radiation tolerance was shown.
なお１、本実施例ではバイポーラトランジスタとして縦
型ｎｐｎ トランジスタが例示されているが。1. In this embodiment, a vertical npn transistor is exemplified as a bipolar transistor.
縦型ｐｎｐ、横型ｎｐｎ、横型ｐｎｐ、ダイオード。Vertical PNP, horizontal NPN, horizontal PNP, diode.
抵抗等のすべてのバイポーラトランジスタに有効である
ことはいうまでもない。また酸化膜としてシリコン酸化
膜、絶縁膜としてＰＳＧ膜を例示したがこれに限定され
ないことはいうまでもない。Needless to say, this method is effective for all bipolar transistors such as resistors. Furthermore, although a silicon oxide film is used as an oxide film and a PSG film is used as an insulating film, it goes without saying that the present invention is not limited to these.
第４図（ａ）、（ｈ）は、第３図に示した本発明の半導
体装置の製造方法の実施例を示す断面図である。FIGS. 4(a) and 4(h) are cross-sectional views showing an embodiment of the method for manufacturing the semiconductor device of the present invention shown in FIG.
まず、第４図（ａ）に示すように、高濃度ｎ形シリコン
層４１上に公知の方法によりｎ形エピタキシャル層４２
を形成する。First, as shown in FIG. 4(a), an n-type epitaxial layer 42 is formed on a highly doped n-type silicon layer 41 by a known method.
form.
次に、ｎ形エピタキシャル層４２表面全面に熱酸化によ
り膜厚２０００λ以上のシリコン酸化膜４３を形成し、
所定の領域に１例えば、シリコン酸化膜４３のウェット
エツチング、不純物拡散及びアニールを繰り返すことに
より、Ｐ形不純物領域４８、高濃度ｎ影領域４９を順次
形成する。シリコン酸化膜４３を公知の方法によりエツ
チングしてすべて除去する。その後、第４図（ｂ）に示
すように１例えば９５０〜１１００℃の高温酸素中で表
面を酸化し、膜厚５０〜２００人のシリコン酸化膜４６
を形成する。次に、リンけい酸ガラス（ＰＳＧ）を例え
ば低温ＣＶＤ法で堆積し、膜厚５００〜３０００人のリ
ンけい酸ガラス膜４７を形成する。Next, a silicon oxide film 43 with a thickness of 2000λ or more is formed on the entire surface of the n-type epitaxial layer 42 by thermal oxidation.
For example, by repeating wet etching, impurity diffusion, and annealing of the silicon oxide film 43 in a predetermined region, a P-type impurity region 48 and a high concentration n-shade region 49 are sequentially formed. The silicon oxide film 43 is completely removed by etching using a known method. Thereafter, as shown in FIG. 4(b), the surface is oxidized in high-temperature oxygen at, for example, 950 to 1100°C, to form a silicon oxide film 46 with a thickness of 50 to 200.
form. Next, phosphosilicate glass (PSG) is deposited by, for example, a low-temperature CVD method to form a phosphosilicate glass film 47 having a thickness of 500 to 3,000.
最後に、各々の所定の位置について、リンけい酸ガラス
膜４７及びシリコン酸化膜４６をエツチングし、電極４
５を設ける０本発明を用いた半導体装置は、平坦な表面
を有するので１段差による配線の切断を防止することも
できる。Finally, the phosphosilicate glass film 47 and the silicon oxide film 46 are etched at each predetermined position, and the electrode 4
Since the semiconductor device using the present invention has a flat surface, it is also possible to prevent wiring from being cut due to a one-step difference.
第５図は本発明の半導体装置の別の実施例を示す断面構
造図である。FIG. 5 is a cross-sectional structural diagram showing another embodiment of the semiconductor device of the present invention.
本実施例の半導体装置は、ｎ形エピタキシャル層５３の
表面に高濃度ｐ影領域５５を有し、横形ｐｎｐ トラン
ジスタを形成し、ｎ形エピタキシャル層５３の表面領域
の高濃度ｐ影領域５５を除いた全面に高濃度ｎ影領域８
０を有している。また、素子の形成された表面に、薄く
平坦な熱膜厚の薄い１例えば５０〜２００人の表面が平
坦なシリコン酸化膜５６を有し、このシリコン酸化膜５
６の表面に、膜厚の厚い、例えば５００〜３０００人の
リンけい酸ガラス膜（ＰＳＧ膜）５７が形成されている
。このような構造のため、電離性放射線照射による固定
電荷の蓄積が減少し、界面の影響が抑えられると共に、
ｎ形エピタキシャル層５３の表面近傍における少数キャ
リア密度が、高濃度ｎ影領域８０によって低下し１表面
領域劣化の影響を抑えることができる。具体的にこの効
果の一例を示すと、現状の横形ｐｎｐ トランジスタで
は。The semiconductor device of this embodiment has a high concentration p shadow region 55 on the surface of the n type epitaxial layer 53 to form a lateral pnp transistor, and the high concentration p shadow region 55 on the surface region of the n type epitaxial layer 53 is excluded. High density n shadow area 8 on the entire surface
It has 0. Further, on the surface on which the element is formed, there is a thin, flat silicon oxide film 56 with a thin thermal film thickness, for example, a flat surface of 50 to 200, and this silicon oxide film 5
A thick phosphosilicate glass film (PSG film) 57 having a thickness of, for example, 500 to 3000 layers is formed on the surface of the substrate 6 . This structure reduces the accumulation of fixed charges caused by ionizing radiation irradiation, suppresses the influence of interfaces, and
The minority carrier density near the surface of the n-type epitaxial layer 53 is reduced by the high concentration n shadow region 80, and the influence of deterioration of one surface region can be suppressed. To give a concrete example of this effect, in the current lateral pnp transistor.
電離性放射線照射前に対する照射後の電流増幅率の比が
、約３ Ｘ Ｉ Ｏ’ ｒａｄ相当の吸収線量で約８０
％であったものが１本実施例の半導体装置では、約３
Ｘ １０５ｒａｄ相当の吸収Ｍｃ盆で約８０％となり、
電離性放射線耐量が約１桁向上することが確認された。The ratio of the current amplification factor after irradiation to that before ionizing radiation irradiation is approximately 80 at an absorbed dose equivalent to approximately 3 X I O' rad.
%, but in the semiconductor device of this example, it is approximately 3%.
It is about 80% with an absorption Mc tray equivalent to X 105rad,
It was confirmed that the ionizing radiation resistance was improved by about one order of magnitude.
なお、本実施例ではバイポーラトランジスタとして横型
ｎｐｎトランジスタが例示されているが、横型ｐｎｐ、
°縦型ｎｐｎ、縦型ｐｎｐ、ダイオード、抵抗等のすべ
てのバイポーラトランジスタに有効であることはいうま
でもない。まだ酸化膜としてシリコン酸化膜、絶縁膜と
してＰＳＧ膜を例示したがこれに限定されないことはい
うまでもない。In this embodiment, a lateral npn transistor is exemplified as a bipolar transistor, but lateral pnp,
It goes without saying that this method is effective for all bipolar transistors such as vertical NPN, vertical PNP, diode, and resistor. Although a silicon oxide film is used as an oxide film and a PSG film is used as an insulating film, it goes without saying that the invention is not limited to these.
第６図（ａ）、（ｂ）は、第５図に示した氷見゛明の半
導体装置の製造方法の実施例を示す断面図である。6(a) and 6(b) are cross-sectional views showing an embodiment of Akira Himi's method for manufacturing the semiconductor device shown in FIG. 5. FIG.
まず、第６図（ａ）に示すように、公知の方法により、
ｎ形基板６１上の所定の位置に、高濃度ｎ形埋込層６２
を形成し、次にｎ形エピタキシャルＭ６３を成長させ、
全面にシリコン酸化膜９３を形成する。その後、公知の
方法により、所定の位置にバタニニング、不純物拡散、
アニールを繰り返して、ｐ形分離領域６４．高濃度ｐ影
領域６５及び高濃度ｎ影領域９０を形成する。First, as shown in FIG. 6(a), by a known method,
A high concentration n-type buried layer 62 is formed at a predetermined position on the n-type substrate 61.
, and then grow n-type epitaxial M63,
A silicon oxide film 93 is formed over the entire surface. Thereafter, by a known method, it is subjected to battanning, impurity diffusion, and
Repeat the annealing to p-type isolation region 64. A high density p shadow region 65 and a high density n shadow region 90 are formed.
次に、第６Ｓ （ｂ）に示すように、公知の方法により
、シリコン酸化膜９３を全面除去し、約５０〜２００人
の厚さでシリコン酸化膜６６を熱酸化法により形成する
。その後、リンけい酸ガラス膜（ＰＳＧ膜）６７を５０
０〜３０００λの厚さで例えば低温ＣＶＤ法を用いて形
成する。続いて、各々の所定の位置について、リンけい
酸ガラス膜６７、シリコン酸化膜６６をエツチングし、
電極６８を形成する。Next, as shown in step 6S (b), the silicon oxide film 93 is completely removed by a known method, and a silicon oxide film 66 is formed to a thickness of about 50 to 200 layers by thermal oxidation. After that, 50% of phosphosilicate glass film (PSG film) 67 was applied.
It is formed with a thickness of 0 to 3000λ using, for example, a low-temperature CVD method. Subsequently, the phosphosilicate glass film 67 and the silicon oxide film 66 are etched at each predetermined position.
Electrodes 68 are formed.
第７図は本発明の半導体装置のさらに別の実施例を示す
断面構造図である。FIG. 7 is a cross-sectional structural diagram showing still another embodiment of the semiconductor device of the present invention.
本実施例の半導体装置は、ｎｐｎトランジスタのコレク
タを形成するｎ形エピタキシャル層７３内にベースを形
成する高濃度ｐ影領域７５を有し。The semiconductor device of this embodiment has a high concentration p shadow region 75 forming a base within an n type epitaxial layer 73 forming a collector of an npn transistor.
高濃度Ｐ影領域７５内にエミッタを形成する高濃度ｎ影
領域９４を有し、高濃度ｐ影領域７５の表面近傍に高濃
度ｐ影領域１００を有している。また、素子の形成され
た表面全面に、膜厚の薄い例えば５０〜２００人のほぼ
平坦なシリコン酸化膜７６を有し、このシリコン酸化膜
７６の表面に、。It has a high concentration n shadow region 94 forming an emitter within the high concentration p shadow region 75, and has a high concentration p shadow region 100 near the surface of the high concentration p shadow region 75. Further, a thin, approximately flat silicon oxide film 76 of, for example, 50 to 200 layers is provided on the entire surface on which the element is formed.
低温ＣＶＤ法で形成された膜厚の厚い例えば５００〜３
０００人のほぼ平坦なリンけい酸ガラス膜（ＰＳＧ膜）
７７が形成されている。A thick film formed by low temperature CVD method, for example 500~3
000 almost flat phosphosilicate glass membrane (PSG membrane)
77 is formed.
本実施例の半導体装置においても上記の実施例と同様の
効果を得ることができた。′
なお、上記実施例ではシリコン酸化膜３３゜４６．５６
，６６．７６の膜厚は５０〜２００人であったが、より
好ましい範囲としては５０〜１００人である。またリン
けい酸ガラス膜３６゜４７．５７，６７．７７の膜厚は
５００〜３０００人であったが、より好ましい範囲とし
ては１０００〜３０００人である。In the semiconductor device of this example as well, effects similar to those of the above-mentioned example could be obtained. ' In the above embodiment, the silicon oxide film is 33°46.56
, 66.76 had a film thickness of 50 to 200, but a more preferable range is 50 to 100. Further, the thickness of the phosphosilicate glass film 36°47.57, 67.77 was 500 to 3000, but a more preferable range is 1000 to 3000.
以上説明したように、本発明によれば、電離性放射線照
射による正の固定電荷の蓄積、界面準位の増加を防止し
、トランジスタの電流増幅率の低下を防止することがで
きる。As described above, according to the present invention, it is possible to prevent the accumulation of positive fixed charges and increase in interface states due to ionizing radiation irradiation, and to prevent the current amplification factor of the transistor from decreasing.
第１図は従来の半導体装置の一例を示す断面図。
第２図は従来の別の半導体装置の一例を示す断面図、第
３図は本発明の半導体装置の実施例を示す断面図、第４
図（ａ）、（ｂ）はそれぞれ第３図に示した本発明の半
導体装置の製造方法の実施例を示す工程断面図、第５図
は本発明の半導体装置の別の実施例を示す断面図、第６
図（ａ）、（ｂ）はそ九ぞれ第５図に示した本発明の半
導体装置の製造方法の実施例を示す工程断面図、第７図
は本発明の半導体装置のさらに別の実施例を示す断面図
である。
１１．３１．４１・・・高濃度ｎ形シリコン層。
１２．２３，３２，４２，５３，６３，７３・・・ｎ形
エピタキシャル層、１３，２７，３３，４３゜４６．５
６，６６．７６．９３・・・シリコン酸化膜、１４．２
９，３４，４４，５９，６９．７９・・・多結晶シリコ
ン膜、１５，２８，３５，４５，５８゜６８．７８−・
・電極、２１，５１，６１．７１−ｎ形シリコン基板、
２２，５２，６２，７２・・・高濃度ｎ形埋込層、２４
，５４．６４，７４．７５・・・高濃度ｐ形分離領域、
２５，５５，６５，１００・・・高濃度ｐ影領域、２６
，４９，８０，９０゜９４・・・高濃度ｎ影領域、３６
，４７，５７，６７゜７７・・・リンけい酸ガラス膜。FIG. 1 is a sectional view showing an example of a conventional semiconductor device. FIG. 2 is a cross-sectional view showing an example of another conventional semiconductor device, FIG. 3 is a cross-sectional view showing an embodiment of the semiconductor device of the present invention, and FIG.
Figures (a) and (b) are process cross-sectional views showing an embodiment of the method for manufacturing the semiconductor device of the present invention shown in Figure 3, respectively, and Figure 5 is a cross-sectional view showing another embodiment of the semiconductor device of the present invention. Figure, 6th
Figures (a) and (b) are process sectional views showing an embodiment of the method for manufacturing the semiconductor device of the present invention shown in Figure 5, respectively, and Figure 7 is a further embodiment of the semiconductor device of the present invention. It is a sectional view showing an example. 11.31.41...High concentration n-type silicon layer. 12.23, 32, 42, 53, 63, 73... n-type epitaxial layer, 13, 27, 33, 43° 46.5
6,66.76.93...Silicon oxide film, 14.2
9, 34, 44, 59, 69.79... polycrystalline silicon film, 15, 28, 35, 45, 58°68.78-...
・Electrode, 21, 51, 61.71-n type silicon substrate,
22, 52, 62, 72...high concentration n-type buried layer, 24
, 54.64, 74.75...high concentration p-type isolation region,
25, 55, 65, 100...high density p shadow area, 26
,49,80,90°94...high density n shadow area, 36
,47,57,67°77...phosphosilicate glass film.
Claims (1)
ル成長層と、該エピタキシャル成長層に設けられたベー
ス領域と、該ベース領域内に設けられたエミッタ領域と
を有するバイポーラトランジスタにおいて、 上記エピタキシャル成長層の上部全面に設けられた厚さ
約１００Åのシリコン酸化膜と、該シリコン酸化膜の上
部全面に設けられた厚さ約 ２０００ÅのＰＳＧ膜とを有し、 上記ベース領域の表面全面には該ベース領域と同一導電
型で該ベース領域より濃度の高い領域が設けられてなり
、 上記エミッタ領域及び上記エピタキシャル成長層夫々と
配線の接触部分には多結晶シリコンを介在して成ること
を特徴とする半導体装置。 ２、半導体素子の形成された基板表面において、少なく
とも該半導体素子形成領域表面を覆う酸化膜を全面除去
し、９５０℃以上の高温条件下で膜厚５００Å以下の第
１の酸化膜を形成し、上記第１の酸化膜上に、５００℃
以下の低温条件下で膜厚２０００Å以上の第２の酸化膜
を形成する工程と、電極取り出し領域について上記第２
の酸化膜と第１の酸化膜をエッチングにより除去し、導
体配線用導電体を上記第２の酸化膜上及び電極取り出し
領域となる該基板表面に蒸着し、配線のパターニングを
行う工程と、上記導電体をマスクとして、エッチングに
より上記第２の酸化膜を除去する工程とを含むことを特
徴とする半導体装置の製造方法。[Claims] 1. In a bipolar transistor having a semiconductor substrate, an epitaxial growth layer provided on the substrate, a base region provided in the epitaxial growth layer, and an emitter region provided in the base region , a silicon oxide film with a thickness of about 100 Å provided on the entire upper surface of the epitaxial growth layer, and a PSG film with a thickness of about 2000 Å provided on the entire upper surface of the silicon oxide film, and the entire surface of the base region. is provided with a region having the same conductivity type as the base region and having a higher concentration than the base region, and polycrystalline silicon is interposed at the contact portion between the emitter region and the epitaxial growth layer and the wiring. semiconductor device. 2. On the surface of the substrate on which the semiconductor element is formed, at least the oxide film covering the surface of the semiconductor element formation region is completely removed, and a first oxide film with a thickness of 500 Å or less is formed under high temperature conditions of 950° C. or higher; 500°C on the first oxide film.
The process of forming a second oxide film with a thickness of 2000 Å or more under the following low temperature conditions and the second
removing the oxide film and the first oxide film by etching, depositing a conductor for conductor wiring on the second oxide film and the surface of the substrate that will be the electrode extraction area, and patterning the wiring; A method for manufacturing a semiconductor device, comprising the step of removing the second oxide film by etching using a conductor as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063425A JPS61224355A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063425A JPS61224355A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61224355A true JPS61224355A (en) | 1986-10-06 |
Family
ID=13228918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60063425A Pending JPS61224355A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61224355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119451141A (en) * | 2025-01-08 | 2025-02-14 | 电子科技大学 | A double-layer STI structure for radiation-hardened bipolar device |
-
1985
- 1985-03-29 JP JP60063425A patent/JPS61224355A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119451141A (en) * | 2025-01-08 | 2025-02-14 | 电子科技大学 | A double-layer STI structure for radiation-hardened bipolar device |
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