JPS61221966A - Vector instruction processor - Google Patents

Abstract

PURPOSE:To minimize the idle time due to a data waiting time by prefetching the mask vector data and supplying this data at a high speed to a processing part from a mask vector data buffer. CONSTITUTION:A memory 10 stores a mask vector containing plural mask vector data. These data are successively prefetched by a mask vector data buffer 11 from the memory 10 and read by a mask vector data reading part 30a. These vector data are collectively processed by a mask vector data processing part 40. While an arithmetic unit 60 and an address producing part 50 are connected to the memory 10 and the part 40 respectively. The actions of these parts are controlled by a controller 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector instruction processing device, and more particularly to a vector instruction processing device that controls execution of vector operations using -gtsc bits for each vector element.

[Conventional technology]

Conventional vector instruction processing devices need to be able to process a wider range of types of processing at high speed in order to greatly improve the processing performance of vector processors.
How to process DO loops containing IF statements at high speed in ORTRAN programs has been an issue, and methods have been devised for a long time to control and process operations using mask vectors.

To briefly explain the concept of the processing process using mask vectors in the DO loop with reference to Figure 2, this DO loop performs operations between the vector elements of vector operand C(I) and vector operand D(I). Make a comparison of
The vector elements of vector operand C(I) that are smaller than the value of vector operand D(I) are
This is an example in which processing is repeated for iN sets of vector elements in which the process is replaced with the addition result of corresponding vector elements of operands A(I) and B(I).

First, we compare the vector element correspondence of vector Q operands C(I) and D(I), and find that C(I) > D(I
), a bit string is created that indicates a value of 10", and when C(I) < D (I), a bit string that indicates a value of 11" is created. This bit string is a mask vector, and each bit is called a mask bit. Then, according to this created mask vector, the vector elements of the vector operands A(I) and B(I) corresponding to the mask bit whose value is 11" are added together, and the result t C(I) is Write to the corresponding vector element. Other vector operands C
(I), that is, the vector element of the vector operand C(I) corresponding to the mask bit whose value is ``O'' is unchanged.

As described above, calculations using mask vectors are performed. When creating mask vectors, if multiple sets of the same type of comparators are prepared, the comparators can be created at once at a higher speed than K. Is possible. Therefore,
In order to process vector calculations using mask vectors at high speed, it is important to process mask vectors that are sequentially created in batches at high speed and perform calculation processing.

For this reason, as shown in FIG. 3, conventional vector instruction processing devices read only valid vector elements indicated by mask bits at the time of requesting a vector element read request, and vector elements whose operations are suppressed. By inhibiting the reading of K, invalid operations are skipped.
There is a vector instruction processing device.

In this conventional vector instruction processing device, vector
A mask vector consisting of a number of mask bit strings corresponding to the number of elements of the operand is divided into certain processing units, and 9 mask vector data'f: 1
In order to sequentially perform high-speed processing as a processing unit, mask vectors that are sequentially created in batches are temporarily stored in a storage device prior to arithmetic processing using mask vectors. When the storage of the mask vector in the storage device is completed, or in parallel with the storage operation, an instruction to start arithmetic processing using the mask vector is issued to the vector instruction processing device. When the vector instruction processing device receives this instruction,
First, vector operand addresses (VHI, 2 and VH3) corresponding to vector operands 1, 2 and 3.
into vector address registers 51, 52 and 53, respectively.

Vector interelement distances (VII, 2 and 3) corresponding to vector operands 1, 2 and 3 are initialized in vector element distance registers 54, 55 and 56, respectively. The control device 20 issues a command to the mask vector data reading section 30.

The mask vector data reading unit 30 issues a mask vector data read request to the storage device 10. Upon receiving the mask vector data read request, the storage device 10 reads the corresponding mask vector data and stores the mask vector data.
The data is sent to the data processing unit 40. In the mask vector data processing section 40, processing is performed based on mask vector data.

FIG. 4 shows the process of processing mask vector data and the procedure for generating addresses of vector elements corresponding to operation instruction bits. Within one vector instruction, adding a constant vector element distance (VIi) to the vector operand address (VHi) yields the vector operand address of the next vector element. Here, referring to FIG. 4 1al, the value of the read mask vector 0 data of bit length (n+1) is % 3
Bit.

The 8th bit..., the (n-3)th bit is the operation instruction bit 11" (the number of bits is fm), and the others (
All DCn-m+1) bits are operation inhibit bits ″″
The vector operand address (VHi, o) is the address of the vector element corresponding to the θ-th bit of the mask vector data.・Address of the vector element corresponding to the third bit of data (VHi
, a) is VHi, 3-VHi, 6+3XVI
Obtained by i. Here, the distance between vector elements (VI i
) is the first operation instruction bit from the beginning (Oth bit) of the mask vector data in Figure 4 (al).
It is obtained by counting the number of operation inhibit bits ``0'' until ``1'' is found.Furthermore, the address (VHi, s )'1, the mask vector data in Figure iE4 (as shown in BL, Figure 4 Ta) is shifted to the left by 3 bits corresponding to the multiplier, and the calculation of the 3rd bit is accordingly performed. The instruction bit ""1" is inverted and used as mask vector data to be used next. At this time, input the logic level ""1" to the shift-in. In this way, the 9 m
Figure 4 (A new table multiplier of 5 is obtained by counting the number of operation suppression bits ""0" t from the beginning to the mask vector 0 data of bl until the υ operation instruction bit @1" is found again. and the address (VHi) of the vector element corresponding to the 8th bit in FIG. 4 1al.

8) is VHi, 8. , vHi, s+5xvxi.

By repeating the above operation 't-m times, the (n-3)th bit operation instruction bit @1' in Figure 4 1a) as shown in Figure 4 10) is inverted and the leading bit is Mask vector data shifted in position is obtained. The vector element address (VHi, o') obtained by performing the same operation once again on the mask vector data of FIG. , is the address of the vector element corresponding to the first bit of the next consecutive new mask vector data.

The above operations are repeated until the multipliers obtained in each operation are added each time, and the resulting added value matches the bit length (n+1) of the read mask vector data. When a match is detected, , ends the processing of one mask vector data.

Refer again to Figure 8g3. The mask vector data processing unit 40 performs an operation of counting the number of arithmetic inhibition bits @"0" until the arithmetic instruction pick @1" is overcome on the mask vector data supplied thereto, as described above. is performed, and the obtained value is sent to the address generation unit 50 as a multiplier of the vector element distance VIi.The multiplier of the vector element distance VIi sent to the address generation unit 50 is 1 multiplier 57, and the selector S5
The vector element distance Vli of the selected vector operand is multiplied by 0 to generate an address difference and sent to address adder 58 . Address adder 5
8, the 9 address difference generated by the multiplier 57 is added to the vector operand address VHi of the corresponding vector operand selected by the selector 854 to obtain the address of the vector element on which the operation is to be performed and stored. For the device 10.

A vector element operand request is sent.

At the same time, the vector address register (51, 52 or 53) of the corresponding vector operand is sent through one of the selectors 851, 52, and
) is updated. When the storage device 10 receives an operand request for a vector element, in the case of a read request, the storage device 10 reads the corresponding vector element and sends it to the arithmetic unit 60. For a multiplier of one vector element distance VIi, operands 1, 2, . and 3, the multiplier of the new inter-vector element distance VIi is supplied from the mask vector data processing unit 40 to the address generation unit 50. . When it is detected that the multiplier of the vector element distance Vli generated by the mask vector data processing unit 40 corresponds to the distance to the first bit position of the next consecutive mask vector data, the control It is reported to the device 20 and one or more series of operations are completed. It is generated by a multiplier of the vector element distance VIi corresponding to the distance to the first bit position of the next consecutive mask vector data sent to the address generation unit 50. The address of the vector element is
0 command, the value of the vector address register (51, 52 or 53) is changed to the first bit position of the next consecutive mask vector data without being used as an operand request to the storage device 10. It is used only to update the address of the vector element corresponding to .

In parallel with this operation, the control device 20 sends a command to the mask vector data reading unit 30 to read out the next consecutive mask vector data to execute sequential processing, and continues processing. Start.

[Problem that the invention seeks to solve]

In the conventional vector instruction processing device described above, the mask vector data processing unit waits for the processing of one mask vector data to be completed and then processes new mask vector data to be processed next. Fetching from storage. Therefore, the mask vector data processing section is forced to wait without being able to process the mask vector data until it is retrieved from the storage device and sent to the mask vector data processing section. Processing also has the disadvantage that idle time occurs during which no processing can be performed, and performance degradation due to access latency of the storage device becomes significant.

[Means for solving problems]

According to the present invention, a storage device that stores a mask vector composed of a certain plurality of mask vector data;
It includes a mask vector data processing section that processes the mask vector data all at once, and a mask vector data reading section that reads out the mask vector data, and the mask vector data is processed by mask bits for every nine elements of the vector. In a data processing device that controls execution of calculations.

a mask vector data address register that holds the address of the mask vector data that is sequentially processed; a mask vector data read data width register that holds the read data width value of the mask vector data; and the mask. - said mask having an address adder for creating an address of preceding mask vector data to be sequentially processed on said storage device from a vector data address and a read data width value of the mask vector data;・The mask vector data processing unit includes a vector data reading unit and a mask vector data buffer that sequentially prefetches the mask vector e data from the storage device and stores the data processing unit. requires the mask vector data, the mask vector O data
A vector instruction processing device is obtained, characterized in that the buffer supplies the corresponding mask vector data to the mask vector data processing section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a vector instruction processing device which is an embodiment of the present invention. In FIG. 1, there is shown a storage device 10 for storing mask vectors composed of a plurality of mask vector data that are included in this embodiment, and
A mask vector data buffer 11 that pre-fetches vector data one after another and stores the data; a mask vector data reading section 30a that reads out the mask vector data sound; It also includes a mask vector data processing unit 40 that performs batch processing.

The storage device 10 stores mask vectors composed of a plurality of mask vector data, vector elements of a plurality of vector operands, and the like. The mask vector data buffer 11 is a dedicated data buffer that holds a plurality of mask vector data. The mask vector data processing section 30g is a mask vector data reading section for reading out preceding mask vector data that is sequentially processed, and includes a selector 830 and a mask that holds the address of the mask vector data. - Holds the vector data address register 31 and the read data width value of mask vector data. It consists of a mask vector data read data width register (hereinafter abbreviated as read data width register Sakaki) 32 and an address adder 33 that adds the output signal of the address register 31 and the output signal of the read data width register 32. ing.

Furthermore, in this embodiment, the storage device 10 is used.

The connected arithmetic unit 60, the address generation unit 50 connected to the mask vector data processing unit 40, and the read pointer of the mask vector data buffer 11 (hereinafter abbreviated as mask vector data pointer) 7
0, and a control device 20 that controls these and each part.

When this embodiment receives an instruction to start arithmetic processing using a mask vector, it sets an initial value, and the mask vector data address register 31 has a selector 530.
f: The address corresponding to the first mask vector-data to be processed is set, and the initial addition value ""0" is set in the read data width register 32. At the same time as the initial value is set, According to the command from the control device 20,
The initial value of the mask vector data address register 31 and the initial added value of the read data width register 32 “O”
# is added by the address adder 33 to generate the address of the first mask vector gator to be processed,
A request to read the mask vector gator is issued to the storage device 10.

At this time, the control device 20 simultaneously sets the read data width value of the mask vector data in the read data width register 32. Thereafter, the read data width register 32 holds the read data width value of the mask vector data. The read data width value of this mask vector gator is unique to each vector instruction processing device in the storage device 10.
It can be set arbitrarily to correspond to one data length read from.

Upon receiving the mask vector data read request, the storage device 10 reads the target mask vector data from the corresponding address.
The vector data is read and sent to the mask Φ vector data buffer 11. The mask vector data buffer 11 holds the mask vector AA data until the mask vector gator processing section 40 uses it.

In this manner, the present embodiment completes the fetch operation of the first mask vector data to be processed.

Originally, mask vectors are stored continuously on the storage device 10, and the mask vector is divided into certain processing units as mask vector number data, and the size of a certain processing unit is determined by the mask vector. It can be made to correspond to the read data width value of the vector gator. Therefore, by sequentially adding the read data width value of the mask vector data to the address of one mask vector gator, the address of the preceding mask vector gator can be generated. The first mask/vector to be processed
When a data read request is issued, the control device 20 continues to hold the value of the mask vector data address register 31 and the read data width register 32 in order to read new continuous mask vector data from the storage device 10. The address adder 33 adds the read data width value of the current mask ψ vector gator to generate a new continuous mask vector data address, and adds a new continuous mask vector data width value to the storage device 10. - Send a vector data read request. At the same time, the control device 20 selects the mask vector gater address register 31 through the selector S30.
The value of is updated.

By repeating this operation, the mask vector data to be processed sequentially is fetched, and the mask vector data is
Before the data processing unit 40 issues a request to use mask vector data, a plurality of mask vector data are stored in the mask vector data buffer 11. The mask vector data processing unit 40 processes the mask vector data.
When one mask/vector gator is required for vector gator processing, a request for mask/pect or data is issued to the control device 20. This request control device 20 uses a mask vector data pointer 70.
The stored mask fist vector data is supplied to the mask vector data processing unit 40 from the corresponding position in the mask vector data buffer 11 indicated by .

After supplying the corresponding mask/vector gator.

The control device 20 has a mask vector gator pointer 70.
is updated to point to the next mask vector data stored in the mask vector gator buffer 11 to be used.

The mask vector data supplied to the mask vector data processing unit 40 is converted into an operation instruction bit @1”K by counting the number of operation inhibit bits @0” in the mask vector data processing unit 40. A process is performed to calculate the multiplier of the distance VIi between vector elements in order to generate only the address of the vector element for which execution of the corresponding operation has been instructed. Since the operation is the same and is not the gist of the present invention, the explanation will be kept brief.

The multiplier of the vector element distance VIi calculated by the mask vector gator processing unit 40 is sent to the address generation unit 50, which generates the address of the target vector element, and sends an operand request to the storage device 10. be done. The storage device 10 reads the corresponding vector element and sends it to the arithmetic device 60. The arithmetic unit 60 stores the arithmetic result in the corresponding location on the storage device 10 corresponding to the data request issued in advance.

In the above operation, the control device 20 prefetches the mask vector gator, supplies the mask vector data to the mask vector gator processing unit 40, and requests the storage device 10 for operands of vector elements instructed to perform operations. control the transmission of the calculation results so that they are performed independently and in parallel, and the storage device 10 for the calculation results.
The data storage is also controlled so that it is performed independently of these three operations.

〔Effect of the invention〕

As explained above, the present invention creates the address of the preceding mask/vector gator to be sequentially processed from the address of the mask/vector gator and the read data width value of A4 data, and Before the Gator processing unit needs the mask vector data, it performs a preliminary fetch of the mask vector data one after another and stores it in a dedicated mask vector data write buffer.

When the mask vector gator processing section requires mask vector data, the corresponding mask vector vector data is supplied from the mask vector gator buffer to the mask vector gator data processing section at high speed. By making this possible, it is possible to minimize play in the mask/vector contest data waiting time in the mask/vector gator processing section, and there is an effect that high-speed continuous processing of mask/pect A4 data is possible. Additionally, the idle time due to vector element waiting time in the arithmetic unit can be significantly reduced, and the efficiency of use of the arithmetic unit can be further improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 2 is a block diagram showing an example of a FORTRAN program in which calculations are controlled by mask vectors and processing is performed; %wca is a block diagram showing a conventional device; Figure 4 shows the mask sound vector ν
FIG. 3 is a diagram showing a data processing process and a procedure for generating addresses of vector elements corresponding to operation instruction bits. 10...Storage device, 11...Mask
Vector data buffer, 20...control device, 30a...mask Φ vector data reading section, 40...mask mask) 7w data processing section, 50...・Address generation section, 60...
... Arithmetic unit, 70 ... Mask vector data read pointer % 31 ... Mask vector data address register, 32 ... Mask mask) A4 data read data width register, 51
, 52.53...Vector-address register, 54,55.56...Vector element distance register, 33,58...Address adder, 57
...multiplier, 830, 850, 851, 852
゜' 853,854...Selector. 〆・') Agent Patent Attorney Uchi Rin Jinwar 2nd page DOyo ItfJ IFCC (O, C7, D (Enon C (L) - A (Enona b (Eng) 10 C0N71NUF-) 3 top V4 @ Procedural amendment ( spontaneous) ◇

Claims (1)

[Claims] a storage device that stores a mask vector composed of a plurality of mask vector data; a mask vector data processing unit that processes the mask vector data collectively; and a mask vector data reading section for reading data, and a mask holding addresses of the mask vector data to be sequentially processed in a data processing device that controls execution of vector operations using mask bits for each vector element. - Vector data address register, mask vector data read data width register that holds the read data width value of mask vector data, and the mask vector data address and read data width value of mask vector data. and the mask vector data reading section having an address adder for creating an address of preceding mask vector data to be sequentially processed on the storage device from the storage device; a mask vector data buffer that sequentially pre-fetches the data and stores the data, and when the mask vector data processing unit needs the mask vector data, the mask vector data buffer stores the data. A vector instruction processing device characterized in that the mask vector data is supplied from a buffer to the mask vector data processing section.