JPS61216593A - Communication channel control memory access system - Google Patents

Abstract

PURPOSE:To attain the access of a communication channel control memory without wasting a limited address space by placing two registers having a bit length of (n-m) or above for writing and reading on a data bus when a bit length (m) of the data bus of a processor is smaller than the bit length (n) of the channel control memory. CONSTITUTION:When the bit length (m) of the data bus of the processor 1 is smaller than the bit length (n) of the channel control memory CM, an (n-m) bit writing register 3 and an (n-m) bit reading register 4 are placed for the channel control memory CM on the data bus of a processor CP. A writing to the channel control memory is carried out by at first writing a part (n-m bit) of the data in the writing register 3, then, writing a remaining data (m bit) in the channel control memory CM. As for the reading, the channel control memory CM is read at first, to obtain a data having (m) bit. At this time, in the reading register 4, the data of (n-m) bit is accumulated. Subsequently, the reading register 4 is read to obtain a remaining (n-m) bit data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a call path control fl memory access system for writing/reading from and to the call path control memory in a time division switch.

As shown in Figure 2, the time division switch has a net leak of N-
It consists of a processor CP and a processor c.
P handles call processing, and when a subscriber makes a call, the CP detects and closes the network N-. Kome Network N
- Inside there is a speech path memory SPM and a control memory (communication path control device) CM, which is a professional '+! □
Tsusa CP is located below the communication path control memory, reads/writes the communication path control memory side, and writes the communication path control memory C.
The speech bus memory SPM switches according to the contents of M. Note that there is a difference in the bit length of data handled by the processor J'CP and the bit length handled by the channel control memory CM, and in order to absorb this difference, a signal is There is a reception distribution device SRD.

There is a need for a communication path control memory access system that configures this SRD with a minimum circuit and does not waste the limited address space.

[Conventional technology]

Conventionally, in a space division switch, the CP system shelf on which the processor CP is mounted and the NW system shelf on which the signal reception distribution device SRD is mounted were separate and connected by cable a as shown in Figure 3, but recently, In time-sharing exchanges where the equipment has been miniaturized and digitalized, the processor CP and the call path control memory side are often mounted on the same shelf or package b as shown in Figure 4, and the logical connection is also strong. It has become.

Figure 5 is a diagram showing the connection of the CP system and SP system of the time division switch.The processor bus includes data bus 1 and address bus 2.
A main memory, an input/output control device 10C, and a communication path control memory CM are installed on the data bus 1.

[Problem that the invention seeks to solve]

Regarding the bit length of the data handled by the processor CP of the above-mentioned time division switch and the bit length of the channel control memory CM, the bit length of the channel control memory CM is determined by the SPM or sp system, and the bit length of the processor CP is used. Since it is a processor bit, there is naturally a difference in bit length.

As a means of solving this problem, considering the case of the channel control memory CM, the channel control memory CI'l is set to n bits, and the processor CP is set to m bits.For example, if 2m=n, the processor CP is set to the channel control memory CM. Only m bits of CM can be read/written. For this reason, there is a method of providing twice the address space on the channel control memory side. This has the problem of wasting limited address space.

[Means for solving problems]

The above problem arises when the bit length m of the data bus of the processor is smaller than the bit length n of the communication path control memory.
B is installed on the data bus, and writing to the call path control memory is performed by first writing part of the data to the register A, and then writing the remaining data to the call path control memory. Reading the channel control memory is solved by the channel control memory access method of the present invention, which first reads the channel control memory to obtain some data, and then reads register B to obtain the remaining data.

[Effect]

That is, if the bit length of the processor is m and the bit length of the communication path control memory is n, write registers and read registers of n-m bits are installed on the processor bus between the communication path control memory and the communication path control memory. To write to the control memory, first write part of the data (n-m bits) to write register A, and then write the remaining data to the communication path control memory to perform the write operation for n bits. To read data from the channel control memory, first read the channel control memory to obtain m bits of data, and then read register B for reading to obtain the remaining n-m bits of data without wasting address space. Data can be obtained.

〔Example〕

Hereinafter, the gist of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram illustrating an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, 1 is a processor bus (data bus). The bit length m of the data bus of the processor bus is
If it is smaller than the bit length n of the channel control memory CM,
In the present invention, an nm-bit write register 3 and an nm-bit read register 4 are installed on the data bus of the processor CP between the communication path control memory CM.

To write to the channel control memory CM, first part of the data (n-m bits) is written to the write register 3, and then the remaining data (m bits) is written to the channel control memory port. At this time, by writing the data (n-m bits) stored in the write register 3 at the same time, a write operation for n bits is performed.

Further, for reading, first, the communication path control memory CM is read to obtain m-bit data. At this time, read register 4
n−m bits of data are stored in the memory. Subsequently, the read register 4 is read to obtain the remaining n-m bits of data.

By providing the read register 3 and write register 4 on the bus of the processor CP between the channel control memory CM as described above, the limited address space is not wasted and the channel control memory You can access the side.

Note that the read/write register 3.4 only needs to be 1 byte. For example, if the channel control memory CM is IK bytes, the address space that would have required 2 bytes in the past would be reduced to the minimum of (IK+1) bytes. This has the effect of requiring only a circuit configuration.

〔Effect of the invention〕

As explained above, according to the present invention, the economical minimum circuit configuration allows access to the communication path control memory without wasting the limited address space, which is very effective.

[Brief explanation of drawings]

, FIG. 1 is a block diagram illustrating one embodiment of the present invention, FIG. 2 is a block diagram illustrating a time division switch, and FIG. 3 is a diagram illustrating cable connections between a CP shelf, NW, and SRD shelf. Figure 4 is a diagram illustrating a state in which processors CP, NW, and SR ports are mounted on the same shelf or package, and Figure 5 is a diagram illustrating the combination of the CP system and N- system of a time division switch. In the figure, 1 indicates a bus of the processor CP, 3 indicates a write register, and 4 indicates a read register. vi Kunihoki 2 (3P30 early 4th ward tea 5 mouths

Claims (1)

[Claims] A communication path control memory for controlling a communication path is installed on a processor bus for performing call processing in which a main memory etc. is installed, and writing/reading of the communication path control memory is performed using the same access method as that for the main memory. In the time division switching system, the bit length m of the data bus of the processor is
is smaller than the bit length n of the communication path control memory, registers A and B for writing and reading having a bit length of n or more are installed on the data bus, and Writing is performed by first writing part of the data to the register A, and then writing the remaining data to the communication path control memory.Reading from the communication path control memory is performed by first reading the communication path control memory and writing part of the data to the communication path control memory. A communication channel control memory access method characterized in that data is obtained, and then the register B is read out to obtain the remaining data.