JPS61213954A - Bus monitor - Google Patents

Bus monitor

Info

Publication number
JPS61213954A
JPS61213954A JP60055551A JP5555185A JPS61213954A JP S61213954 A JPS61213954 A JP S61213954A JP 60055551 A JP60055551 A JP 60055551A JP 5555185 A JP5555185 A JP 5555185A JP S61213954 A JPS61213954 A JP S61213954A
Authority
JP
Japan
Prior art keywords
bus
signal
generating circuit
refresh
occupying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60055551A
Inventor
Masahiro Ono
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP60055551A priority Critical patent/JPS61213954A/en
Publication of JPS61213954A publication Critical patent/JPS61213954A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To prevent troubles in main storage refreshing operation from occurring by refreshing a main storage preferentially when there is an input/output device which occupies a bus for longer than one refresh period and identifying the device at this time.
CONSTITUTION: A refresh counter 7 which counts a refresh period drives a refresh address generating circuit 8 for the main storage to output a refresh address to a common bus 6 when a bus occupying signal generating circuit 9 generates a signal for occupying the common bus 6. The bus occupying signal generating circuit 9 holds the bus occupying signal with a signal WAIT from a wait signal generating circuit 0 when a bus occupation extension signal BSWAIT arrives from an input/output device, etc., but when an end signal generating circuit 11 detects a specific time elapse from the generation of a refresh request, the signal WAIT is stopped and refreshing operation is performed.
COPYRIGHT: (C)1986,JPO&Japio
JP60055551A 1985-03-19 1985-03-19 Bus monitor Pending JPS61213954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60055551A JPS61213954A (en) 1985-03-19 1985-03-19 Bus monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60055551A JPS61213954A (en) 1985-03-19 1985-03-19 Bus monitor

Publications (1)

Publication Number Publication Date
JPS61213954A true JPS61213954A (en) 1986-09-22

Family

ID=13001837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60055551A Pending JPS61213954A (en) 1985-03-19 1985-03-19 Bus monitor

Country Status (1)

Country Link
JP (1) JPS61213954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6684278B1 (en) 1999-07-16 2004-01-27 Mitsubishi Denki Kabushiki Kaisha Microcomputer and memory access control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6684278B1 (en) 1999-07-16 2004-01-27 Mitsubishi Denki Kabushiki Kaisha Microcomputer and memory access control method

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