JPS61208548A - Microprocessor analyzer - Google Patents

Microprocessor analyzer

Info

Publication number
JPS61208548A
JPS61208548A JP60049657A JP4965785A JPS61208548A JP S61208548 A JPS61208548 A JP S61208548A JP 60049657 A JP60049657 A JP 60049657A JP 4965785 A JP4965785 A JP 4965785A JP S61208548 A JPS61208548 A JP S61208548A
Authority
JP
Japan
Prior art keywords
trace
level
data
counter
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60049657A
Other languages
Japanese (ja)
Inventor
Yoshio Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP60049657A priority Critical patent/JPS61208548A/en
Publication of JPS61208548A publication Critical patent/JPS61208548A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To record accurately the data immediately before and after each trace word by storing only the trace work which is regarded as the factor of an abnormal phenomenon into a trace memory.
CONSTITUTION: A trace word pulse Twp is applied as the trace data after the records dm-1 and dm, and a delay counater 4 starts counting. Then the carry out C is set an H level when the count value of the counter 4 reaches a prescribed level. Thus a synchronizing counter 3 is replaced with the address areas of B1WBn of a trace memory 1. Then a synchronizing counter 2 is set at '0' when the output C is set at an H level and therefore shifted to the head address B1 of those addresses B1WBn. Then the data to be executed by a target microprocessor are recorded successively in the areas B1WBn.
COPYRIGHT: (C)1986,JPO&Japio
JP60049657A 1985-03-13 1985-03-13 Microprocessor analyzer Pending JPS61208548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60049657A JPS61208548A (en) 1985-03-13 1985-03-13 Microprocessor analyzer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60049657A JPS61208548A (en) 1985-03-13 1985-03-13 Microprocessor analyzer

Publications (1)

Publication Number Publication Date
JPS61208548A true JPS61208548A (en) 1986-09-16

Family

ID=12837253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60049657A Pending JPS61208548A (en) 1985-03-13 1985-03-13 Microprocessor analyzer

Country Status (1)

Country Link
JP (1) JPS61208548A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02242345A (en) * 1989-03-15 1990-09-26 Yokogawa Electric Corp Microprocessor/analyzer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02242345A (en) * 1989-03-15 1990-09-26 Yokogawa Electric Corp Microprocessor/analyzer

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