JPS61188942A - Solder connection body and formation thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrical connection between a microelectronic chip and its holding substrate. More specifically, the present invention provides the ability to increase the shear strain of a microelectronic chip during its heating and cooling cycles without exceeding the limits of shear strain allowed in the connections. The present invention relates to novel solder connections and methods of manufacturing such solder connections that are configured to allow use of larger sized microelectronic chips having higher density solder connection matrices.

SUMMARY OF THE DISCLOSURE In accordance with the present invention, microelectronic chips are electrically connected to a substrate by elongated solder posts created with solder dams on the surface of the substrate. Solder dams are provided on at least some of the connection pads on the surface of the substrate. By increasing the length of the solder pillar, the bending of the solder connection body can be increased.
The size of such an extended solder post matrix can be increased considerably without exceeding the shear strain tolerance limits.

[Prior art]

BACKGROUND OF THE INVENTION Over the past two decades, rapid advances in integrated circuit device manufacturing technology have made it possible to implement very complex circuits on a single silicon chip, including a large number of independent circuit elements.

A typical chip for solder connection is a square with a side of approximately 6.4 mm, so it is a connection point for electrically connecting the chip to external circuitry in order to send and receive data or receive and receive operating power. The solder pads need to be very small. FIG. 4 is an enlarged perspective view for explaining a conventional technique generally used for mounting the chip 10 on a substrate, and FIG. 5 is a cross-sectional view thereof. Typically, a silicon chip has microelectronic circuitry on only one side. A matrix of downwardly projecting solder balls 12 for connecting microelectronic circuits is connected in a manner already widely known. Such fine solder balls form controlled collapse connections to the chip 10.
trolled ”coll & pse co
nnection), which is usually O in this field.
-4 connection or O-4. The O-4 solder balls are placed in contact with a substrate 14 having a corresponding matrix of solder connection pads 16. Solder connection pads 16 are substantially coplanar with the top surface of the substrate.

Substrate 14 can be a multilayer ceramic structure of the type described in U.S. Pat. No. 4,245,273. Such a board includes peripheral connection pads 18, input/output and power pins (not shown) on the underside of the board, and conductive tracks 20, 24 extending horizontally and vertically. Conductive path 20
．． 24 extend through the interior of substrate 14 to interconnect chip 10 and connection pads 16 to various input/outputs and power supplies as desired. An example of such a board is
IBM Journal of Research, January 1982
and development (More M Journal
ofResearch and Developo
“Thermal Transfer Module: High Efficiency Multilayer Ceramic Package” (Therma) in Tol, 26, & 1
lConductionModule: A Hlg
h Performance Multi-1aye
Blodgett and Barba (B!Lr.
bour) literature (pages 30 to 36), and 198
From April 2019, MTDB (More M Techn
icalDisclosure Bulletin)
Hubaher's document entitled “Shared ECC Pad Design” in Vol. 24, AIIA (Vol. 5).
554 to 5557).

In order to connect the chip 10 to the substrate 14, ha! 4-J
-1-+-ru 1 ri Qing (jinchu name C)gu・so 1. ”
1-1-The ambient temperature is raised to the melting temperature of the solder, and the solder is reflowed to form the mold of the short connecting post 26 as shown in FIG. reflow). Typically in the prior art, the length of such a connecting post 26 is between 0.025 mm and 0.10 mm, or about half the diameter of the solder ball used. The term "solder" as used herein has a melting temperature of 180°C to 320°C, and the main components are lead (40% to 100%) and tin (0%
60%).

[Problem that the invention seeks to solve]

Although 0-4 solder connections have been widely used to connect silicon devices to substrates in the manner shown in Figures 4 and 5, the scope of application of this type of connection has been limited to substrates. They were limited to smaller sized matrices of connections used in chips that required only a few connections. Due to the difference between the thermal expansion of the substrate 14 and the thermal expansion of the chip 10, O
-4 This limitation is due to the shear strains that occur in the connections. The difference between chip expansion and substrate expansion that occurs between room and operating temperatures must be accommodated by the deformation of the solder posts 26.

The range of allowable deformation is governed by the predetermined fatigue life of the connection. The maximum shear displacement position δ of the connection body is given by the following equation when the chip and substrate are at the same temperature. 'In the above equation, L is the outermost dimension of the O-4 connector matrix, α and α5 are the expansion coefficients of the silicon device and substrate, and ΔT is the temperature rise from room temperature to operating temperature. Temperature changes during heating and cooling also result in temperature differences between the chip and the substrate, thus resulting in differences in expansion even when α and α5 are equal. When the height h of the solder pillars 26 increases,
It has been previously recognized that the shear strain γ decreases according to the equation:

δ γ5- Here, δ is the amount of shear displacement of the solder pillar in question.

The performance of the 0-4 connector is determined by reference to the maximum shear strain that the outermost C-4 connector can sustain when operated with a given chip and substrate combination. Therefore,
For a given maximum allowable shear strain, increasing the height h of the C-4 connections will correspondingly increase the overall size of the C-4 connections matrix and reduce the allowable size of the silicon device itself. It increases by attaching it to it. Larger size chips perform more functions on the chip and increase the degree of integration, thereby achieving increased operating speed and manufacturing efficiency.

Known techniques that attempt to increase the length of connections between a chip and its substrate include U.S. Pat.
No. 067,104. However, simply increasing the height of the O-4 connection creates additional interlayers, making it difficult to use larger chips. For example, the potential for electrical shorts between densely packed A-4 connections increases as the connections warp during temperature cycling. It is therefore necessary to avoid the tendency of the 0-4 connections to touch each other when very little space between the connections is required.

The primary object of the present invention is to provide a new O-4 connector structure and method of manufacturing such a connector.

In the present invention, the size of the C-4 connector matrix is increased, and an extended a -4 connector structure is given.

Another object of the present invention is that each connection point dams flowing solder when the chip is attached to a board, either when the solder is first reflowed or when the solder is reflowed to replace the chip. The object of the present invention is to provide a new connector structure including means for.

Another object of the invention is to provide a connector and method of manufacturing the same that can be used with known techniques for manufacturing multilayer ceramic substrates for holding and electrically connecting microelectronic chips.

The present invention provides a method for increasing O-4 connections without increasing the spacing between the connections and without increasing the tendency of longer connections to create electrical shorts. Various techniques for increasing height are provided.

According to one embodiment of the method of the invention, by providing at least some of the connections with dam means surrounding the connections,
Solder connections are formed on a substrate having an electrical connection matrix. The above dam means defines an open space in the center for storing molten solder during mounting of the electronic chip with a corresponding matrix of electrical connections onto the electronic board or during removal of the electronic chip from the electronic board. do.

Molten solder is then introduced into the open space and cooled to form an elongated solder column with exposed connector surfaces within the dam means. To join the substrate and chip, the chip is placed on the substrate such that the solder posts on the substrate are in contact with the corresponding connections of the chip, and the assembly thus formed is heated so that the solder melts. When heated, the solder posts melt and electrically connect the chip to the substrate.

In the structure according to the present invention, a dam means is provided on an electronic board of a type having an IJ rack for electrical connection bodies, surrounding at least a part of these electrical connection bodies, and the dam means defines an open space in the center for storing molten solder during installation of the electronic chip with a corresponding matrix of electrical connections onto the electronic board or during removal of the electronic chip from the electronic board. When the chip and substrate are placed in contact and reflowed at high temperatures, solder posts form electrical connections between corresponding connection points on the chip and the substrate.

In accordance with the method of the invention, a layer of electrically insulating material is provided on the surface of the substrate, surrounding the connection points of the substrate, and a plurality of openings are provided through said layer to define said central open space. By providing the holes, a means for damming the molten solder is formed.

Alternatively, a portion of the electrically insulating material layer may be removed to define a circular solder dam surrounding each central open space. According to a particularly advantageous method embodiment of the invention, the electronic device is a multilayer ceramic substrate carrying a microelectronic chip, and the dam means comprises a plurality of apertures, such that the apertures define a desired central open space. It is formed by preparing a single layer of ceramic material having apertures of , laminating the single layer onto an unsintered multilayer ceramic substrate, and sintering the single layer. The expansion coefficients of the non-ceramic insulator material and solder are chosen such that the apertures forming the dam means at least partially separate from the solder pillars when the solder cools, so that during expansion or contraction Provides an air gap in which the solder pillars can move. This void is also provided by shrinkage that occurs when the solder solidifies.

〔Example〕

Preferred embodiments of the present invention will be described below with reference to the drawings. Like reference numbers represent like elements in each figure of the drawings.

In the connection shown in FIG. 3, the underside of the chip 10 is provided with a layer 28 of photopolymer or photoderivative epoxy, the layer being approximately 0.050 mm to 0.0 mm thick.
．． It has a thickness of 200 mm. Layer 28 may be glued or clamped in place. The via holes 30 are formed using laser drilling technology;
Alternatively, holes may be drilled through layer 28 using photolithography techniques. A polymer sold under the tradename Kapton has been found to be a suitable material for this purpose. Solder is deposited into the via hole 30 to provide a solder ball or solder column having a longer axial dimension than is already known in the prior art.

It is of course possible to increase the height of the solder ball by adding additional solder into the via hole 60. When a chip formed in this manner is bonded to a substrate 14 as shown in FIG.
6, we can use a matrix of more connection points with more densely packed O-4. Layer 28 also serves as a means to at least partially dam the flow of solder during bonding and flow of chip 10 to substrate 14, thereby reducing the possibility of solder spreading causing short circuits.

1 and 2 show an embodiment in which an electrically insulating and easily deformable ring 32 is provided around each connection pad 16 of the substrate 14. FIGS. This structure is useful when the gap between the connection and the surrounding solder dam is small enough to severely impede warpage of the connection during thermal cycling. 1. Conventional photolithography techniques can be used to form ring 32 from a layer of a suitable material, such as a polymer or a thermally stable photosensitive epoxy resin.

After forming the ring 32, the central open space of the ring is
The solder dipping technique, or wave soldering, is well known to experts in the field.
g) Depending on the technology, it can be filled with solder. The ring thus functions as a solder dam as described above.

When the chip 10 shown in FIG. 1 is reciprocated between room temperature and operating temperature, the connector 26 is plastically deformed and the ring 6 is elastically deformed.

Height hl is approximately 0.064 mm, inner radius r
l is approximately o, o 57 mm, and the outer radius r2 is approximately 0.0? The shear strain in the unretained portion of the connector 26 between the ring 62 and the underside of the tip 10 for a 9 mm J meter polymer ring with a center-to-center spacing of 4 times rl. is reduced to about 25%. In this state, the approximately 0.020 mm thick ring 32 is attached to the connecting body 26 as shown in FIG.
Slightly deform the lower part of. This modification of the O-4 connector increases the chip size by about 25% without violating the maximum shear strength limit. It is known that as the thickness of the ring increases, the change in applied shear strain decreases. The calculations described below do not take into account the advantage that the ring and solder shrink away from each other when the ring and solder structure is lowered below the reflow temperature.

As shown in the simple analysis below, an improvement of about 25% can be achieved with the embodiments shown in FIGS. 1 and 2. The balance of shear force on the top surface of each ring 62 is τoπr1−τ1πr1+τPπ(r2−rl)・(
1) is required.

In the above formula, τ. is the shear strain of the unretained portion of the O-4 solder pillar, which is assumed to be a constant value. rl is the radius of the O-4 solder pillar, which is assumed to be a cylinder. τ is the shear strain in the solder within the ring 62, and is assumed to be a constant value. τ2 is the shear strain in the ring 32 and is assumed to be a constant value. r2 is the radius of the outer diameter of the ring 32.

This is because polymers can be treated as perfectly elastic bodies.

In the above equation, μm is the shear modulus of the polymer, δ is the displacement of the top of ring 32, and hl is the displacement of the top of ring 3
The height is 2.

Since the strain in this part within the connecting body 26 is approximately 1%, and the solder material can be considered to be a plastically deformable material due to work hardening, τA+Bγ (3). In the above, ASB and n are constants, and γ
is the shear strain. '5/95 Sn/
Mechanical properties of Pb solder and solder containing impurities" (
5/95Sn/Pb 5older and S
Older Containing
es), Rathore, Iu (
ylh) and IBM Technical Report by Edenfeld (B M Techni)
cal Report) TR22 Yu009 (1970
Based on the information disclosed in 2007), approximate values for AlB and n are 98 kg/cm for A at approximately 1% strain.
, B is 280 kg/cm, and n is approximately 0.5.

Combining equations (1), (2) and (3) leads to:

h −h δ−δ, +δ. Then, 0
It becomes 1゜.

r is 0.057mm, hl and ho are both 0.064mm, μm is 18.1XION/
m2, B is 8.5 × I ON / m”, and the typical maximum displacement of chips currently in use, δ, is 61
．． δ for various values of r2 for 9 × 10 mm. The values of and δ are shown below.

0.095 53. lXl0 9.14XIOO
,860,12256,6XIO5,33XIOO,9
It should be noted that for an array of connection pads having a center-to-center spacing of 0.228 mm, a value of r2 greater than 0.114 mm has no meaning. However, this example can be used to represent the stiffness of a solid polymer layer with cylindrical apertures spaced 0.114 millimeters apart.

δ. The value of /δ gives the degree of reduction in shear strain in the unretained portion of the connector 26 that is not retained by the ring 62 relative to the strain in the standard type connector 26 shown in FIG. . For the thinnest polymer ring with a wall thickness of 0.020 millimeters, the shear strain is approximately 22
% will be reduced. If the size of the O-4 matrix were increased to give the standard maximum allowable shear strain, the new size would be approximately 25% larger than the original size.

Referring to FIGS. 6-15, which illustrate another embodiment of the invention, means are provided for damming the solder. The solder damming means are clearly separated from the solder column at the operating temperature, thus giving the lower part of the solder column greater freedom of movement and reducing shear strains more effectively. A layer 34 of electrical insulator having a coefficient of expansion greater than that of the substrate 14 is provided on the top surface of the substrate 14.

For example, a polymeric plastic layer can be provided having a thickness in the range of 0.05 mm to 0.125 mm. Such a polymeric plastic layer consists of 2
If a 92% alumina (A1203) ceramic was used for the substrate 14, the expansion coefficient α5 of the substrate 14 would be 6.5XIO/.
It is. When an array of vertical, cylindrical via holes 66 as shown in FIGS. 6 and 7 are provided in the layer 64 described above, the top of each via hole 36 is connected to the substrate 14 and the adhesive layer 34 with solder. When the temperature is returned to room temperature from the initial temperature, it will spread out against the bottom of the via hole (see Figure 8).
. This is due to the bi-axial nature in the upper layer, assuming good adhesion between layer 34 and substrate 14.
) caused by tensile strain.

When a substrate with such layer 34 is bonded to chip 10 in the manner shown in FIG. do. This void is created by three elements. (1)
The first factor is shrinkage when the solder solidifies, (11)
The second element is the opening of a hole in the electrical insulator material that responds with a different shrinkage degree to the substrate, and the (111) third element is a similar different shrinkage degree of the solder. The coefficient of thermal expansion of lead solder containing 5% tin is approximately 25XIO/'. Accordingly, both the polymer wall 38 and the solder move away from each other.

The structure shown in FIGS. 6-9 is formed by depositing on the upper surface of substrate 14 a layer of electrically insulating material having a large coefficient of expansion. Apertures with the desired O-4 connection dimensions are provided in this layer. Apertures extend through the top surface of the layer from the solder pads 16 and conductive tracks 20 that electrically connect the O-4 connections. These apertures therefore function as solder dams in the manner already described.

Next, these holes are formed using mask evaporation soldering techniques and blank evaporation including the process of removing excess solder. 1-
+Shiju Tsukuzu Tsukuzu I now? Doushi Z ^〒-Go? →Filled with molten solder by soldering technique or other known soldering techniques. Next, a silicon device provided with regular C-4 solder balls is placed on top of the substrate,
After the solder is reflowed and cooled to room temperature, the structure shown in FIG. 9 is obtained.

Upon cooling from reflow temperature to room temperature, the silicon of chip 10 shrinks less than the ceramic material of substrate 14, so that solder connections 26 are severely distorted, as shown in FIGS. 10-15. When the chip is brought up to its operating temperature, the severely distorted solder connections, ie the solder connections at the periphery of the chip, are removed from the inner wall 38 of the via hole 36, where the connectors are opposite at room temperature. Deformed in the direction of separation. The distance that point p of the O-4 solder post at the level of the top surface of layer 34 moves before it hits the inner wall on the opposite side of via hole 36 is 2Δ', or approximately Δ'. That's twice as much. In this case, Δ' is estimated for the solder pillar 26 in the center of the chip, taking into account the elasticity of the upper part of the via hole 66, the shrinkability of the C-4 solder pillar, and the degree of shrinkage upon solidification.

Because the polymeric material of layer 34 is rigid against the plastically deforming solder material, the G-4 post deforms and closes via hole 66.
It is necessary to avoid contact with the inner wall 38 of the O-
When the '4 solder post comes into contact with the inner wall of the via hole, substantially any further displacement of the chip 10 with respect to the substrate 14 is caused by layer 34, i.e., the O-
It must be adjusted by deformation of the four pillar sections. A 0.127 mm thick polymer layer 64 having an array of via holes 66 with a radius of 0.057 mm and a center-to-center spacing of 0.229 mm, and a solidification temperature of 300'C. for the 5% tin lead solder without exceeding the maximum allowable shear strain and that all O-4 pillars are on the inner wall 6 of the via hole 36
It has been estimated that an increase in chip size on the order of 140% can be achieved with reasonable solder dam thickness without contacting 8. The above-mentioned "reasonable" thickness for a dam is a thickness approximately equal to the diameter of the via hole.

The isolation of the a-4 column provided by the solder dam and which O
It is also possible according to the invention to reduce the size and spacing of the O-4 connections in view of the effective shear strain achieved without impinging on the solder dams. The layer 54 has smaller and more closely arranged apertures.
It is easy to form inside. The solder balls of the chip 10 are made smaller as the distance between the ○-4 connectors becomes closer. For typical chips currently in use, a 0.051 mm thick polymer dam allows for an O-4 pillar radius of 25 mm (Lo) and approximately 0.025 mm Glue. .100
Allows millimeter center spacing.

This reduces the size and spacing of the O-4 connections by approximately 60%.

Chip operating temperature T. In the strain-free type connector shown in FIG. 13, the gap Δ between the inner wall 38 of the via hole 36 and the O-4 column can be estimated by the following equation.

Δ−(α, −α>< T 8T O> r , +(α
8-αρ('r, -'r0) , α8 is the expansion coefficient of the solder, is the solder reflow temperature, r is the radius of the lower part of the via hole 3B as seen in Figure 9, and 4r is the radius between the via holes. IV is the volume shrinkage rate when solder solidifies.

This relationship assumes that the thermal strain in the layer 34 structure, which has a thickness approximately equal to the size of R, is completely relaxed at the upper surface of layer 34.

α and α8 are 25X10/K and T is p

B297°C and T
If is 85°C and rl is 0.057 millimeters, then Δ' is 46 XIO millimeters.

The difference in coefficient of expansion between the chip 10 and the substrate 14 results in an O-4 column, -γλ, in the chip's circumference, and the aspect is as shown in FIG. Four posts are pressed against one side of the via hole 66.

At room temperature TH, such 0-4 pillars are connected to the via hole 36.
The distance that must be traveled to reach the other side of is defined by the following equation:

At the operating temperature of the chip, the distance the C-4 pillar must travel is 2Δ, as shown in FIG.

Therefore, at To, the displacement δ resulting from the chip-to-board expansion mismatch is such that the O-4 pillar
should not be large enough to touch the This relationship is expressed by the following equation.

In the above formula, δ-J"f L<α5-α.)(To-TR)...(9
) and α. is the tip 10 expansion coefficient. The displacement is the maximum allowable shear strain γ of approximately 1%. Therefore, the shear strain must not occur in excess of .

The maximum outer dimension of the matrix of 0-4 columns, the value of L, can be maximized by setting it to 2∆maxγh... (11), which is hl
Set the value to 0.267 millimeters. For this value of h, the value of L would be 18.3 mm, which is the largest chip size currently allowed if a full 0.267 mm solder dam were used. shows an increase of 350%. This requires a larger aspect ratio for the via holes. In a reasonable case, if a 1:1 aspect ratio was used for the via holes, the dam thickness would be 0.127 millimeters and C-4.
The allowable increase in size of the matrix is approximately 140%.

Referring to FIGS. 16-22, which illustrate another embodiment of the present invention, a multilayer ceramic substrate is shown having a unique structure that holds 0-4 pillars in recessed solder dams.

As shown in FIG. 16, the multilayer ceramic substrate includes multiple layers 14a-14e that are assembled and sintered to provide a unitary substrate. For example, the above-mentioned US Pat. No. 4,245,273 discloses a conventional technique for manufacturing such multilayer ceramic substrates. Figures 16 to 2
In accordance with the embodiment of the invention shown in FIG.
and pre-punched to provide a plurality of via holes 66 aligned with the conductive paths 20 and other via holes 42 aligned with the conductive paths 22 and connection pads 18, for example. (See Figure 17). A mask 44 is provided having an aperture 46 that matches the via hole 36 . mask 44
There is no opening at the position corresponding to the via hole 42. Via hole 36 is filled with a flammable material, such as terephthalic acid paste (see FIG. 18). Next, another mask 50 is provided having an aperture 52 that matches the via hole 42 . Mask 50 has no apertures at positions corresponding to via holes 66 .

Via holes 42 are filled with a conductive material such as molybdenum paste. A conductive path 22 is also provided on the surface of layer 40 in a known manner to provide a connection path to pad 18 (FIG. 16). Layer 40 is then laminated to the already assembled multilayer substrates 14a-14e and the second
The structure is sintered as shown in Figure 0. At this time, the combustible material 48 is burned away leaving a via hole 36 which is a space for receiving molten solder. Nickel or gold is plated on the bottom of the via hole 36 to cover the exposed surface of the molybdenum conductive track 20, and then a solder ball is set into the via hole 66 and as shown in FIG. is reflowed to fill via hole 66. Alternatively, it is also possible to fill the via holes 3 with solder and reflow by ultrasound, by immersion in a solder bath, by solder lamination, or by solder evaporation. Temporary protective coatings can also be applied to other sides of the board to avoid solder contamination. Finally, the bottom surface of the ball on chip 10 with a standard O-4 solder ball is placed in contact with substrate 14 so that the solder ball contacts the solder in via hole 66. The solder is then reflowed and an extended O-4 post as shown in FIG. 6 is created.

Via holes 66 are formed in the top layer 40 using an embossing technique that creates a depression having a depth of 0.025 mm to 0.125 mm by pressing the top surface of the conductive path 20 downward with a suitable die. It is also within the scope of the present invention to do so. In some applications, a connector matrix with a much smaller shear strain than the periphery may be used with regular connectors in the center and O-4 pillars with solder dams only at the periphery of the connector matrix.

In the currently used and reliable O-4 design,
Approximately 0.127mm O-4 ball l 7Xl
7) Can be used for IJ socks with a center spacing of 0.254 mm. Looking at the structure shown in Figure 16,
A matrix of indentations with a depth of O, 127 millimeters at currently allowed fatigue strain levels of 42
Can be used to support an X42 A-4 column matrix.

If a conventional 0.127 mm hunter pole is bonded to a 0.127 mm solder post in via hole 36 as shown in FIG. The volumetric shrinkage of the solder during operating temperatures and the different thermal shrinkage rates are approximately -0,015
6 different bond thermal shrinkage coefficients (combin
e d d i f f e r e n t i
a l shrinkage ΔL/L.

For a via hole with a diameter of 0.127 mm,
This shrinkage rate is the same for via holes and O-4 at operating temperatures.
Approximately 99゜1 x 10'' 5mm air gap Δ(
(Fig. 15) occurs. As shown in FIG. 12, the outer O-4 post is warped to an extreme position at room temperature, effectively touching the inner wall opposite the via hole.

In order to ensure that the outer O-4 pillar does not experience excessive shear strain and contact the inner wall opposite its via hole, equations (8) and (9) are used in the embodiment of FIG. and (1o) must be satisfied. In such a case, if γ. -6 to about 0.01.

equal, α5 is equal to 6.5XIO/K, and α
is equal to 2.5XIO/', the maximum lateral displacement of the O-4 column, δ, is approximately 180 x 10 mm. If the maximum number of solder pillars on one side of the solder pillar matrix is n, and the spacing between the centers of solder pillars is a, then the value of B in equation (10) is equal to (n-1) a, so one The maximum number of solder pillars on a side can be about 42 in the present invention, as opposed to 17 in the prior art. The outermost O-4 pillar does not deflect until it contacts the inner wall on the opposite side of its via hole.

FIG. 2z shows a cross-sectional view of another embodiment of the invention, in which the substrate 1
4 is provided with a recess for a solder post of the type shown in FIGS. 16 to 21, while the chip 10 is also provided with a recess for a solder post of the type shown in FIG. It is provided. It is a technique of the present invention to provide such depressions at the connection points of either the chip 10 or the substrate 14, or all the connection points of both the chip 10 and the substrate 14, or only selected connection points. belongs to the range.

〔Effect of the invention〕

As described above, the present invention provides a novel method for manufacturing an O-4 solder connection that provides a solder connection that is superior to the conventional C-4 connection. An improved O-4 connector that allows for higher density and larger size connector matrices, avoids the problem of connectors shorting together, and can be used in larger size and higher density electronic chips. As a result, the degree of integration can be increased, the operating speed of computers, etc. can be improved, and manufacturing efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of an embodiment of the invention in which an annular dam means is provided on the upper surface of the substrate; FIG. 2 shows the deformation of the structure shown in FIG. 1 due to different thermal expansions; FIG. 3 is a partial cross-sectional view of a novel O-4 connection in which dam means are provided on the underside of the tip;
FIG. 4 is an enlarged perspective view for explaining the state before the microelectronic chip and the substrate are combined; FIG. 5 is a partial cross-sectional view for explaining the conventional connection body between the substrate and the microelectronic chip;
FIG. 6 is a partial cross-sectional view of another embodiment in which the dam means is provided by a layer of electrically insulating material on the top surface of the substrate; FIGS. 7 and 8 are views of the structure shown in FIG. FIG. 9 is a partial cross-sectional view of the embodiment of FIG. FIG. 3 is a cross-sectional view showing the deformation of the connector due to different thermal expansions during operation;
FIGS. 10 to 15 are partial cross-sectional views of the embodiment of FIG. 6, illustrating how the inner wall of the dam means is separated from the solder connection, and the reflow temperature, room temperature, and a diagram illustrating the different strains of the connections at the periphery of the chip and at the center of the chip at the operating temperature,
FIG. 16 is a partial cross-sectional view at room temperature of an alternative embodiment structure in which dam means are formed in a multilayer ceramic substrate by providing a final ceramic layer with suitable apertures for receiving solder; Figures 17 to 21 are
FIG. 22 is a diagram illustrating the steps for preparing a substrate of the type shown in FIG. 6; FIG. 22 shows another variant of the embodiment shown in FIG. FIG. 10... Chip, 12... Solder ball, 14
... Board, 16.18... Connection pad, 20.
24... Conductive path, 26... Connection body 4.32...
...Ring, 30.36.42...Via hole. Applicant International Business Machines Corporation Sub-Agent Patent Attorney Shino 1
) Written by Yu 10° Tetsua Figure 2 Small invention

Claims (2)

[Claims] (1) In an electronic circuit component board (for example, 14) having a matrix of electrical connection bodies (for example, 16), interpose a solder ball in alignment with the connection body on the side of the electronic circuit component (for example, chip 10) to be connected. 1. A solder connection body characterized in that a damming means (for example, a ring 32, a via hole 36) made of an electrically insulating material is provided around the periphery, which can store molten solder when the solder is heated. (2) A method of forming a solder connection on an electronic circuit component substrate (e.g. 14) having a matrix of electrical connections (e.g. 16), comprising: an electronic circuit component (e.g. When the chip 10) is mounted on the electronic board and heated, a dam means surrounding each of the connecting bodies and defining an open space in the center is installed in at least a portion of the connecting bodies to store molten solder. Introducing molten solder into the open space, and cooling the molten solder so as to form a solder column having an exposed surface in some of the connection bodies. A method of forming a solder connection body consisting of: