JPS6118836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory that eliminates hazards that appear during memory reading.

In general, a semiconductor memory is composed of a large number of memory cells, an address decoder that specifies the cells, and peripheral circuits such as an output circuit that outputs read data. From such semiconductor memory,
To read the contents stored in memory cells,
It is necessary to input address data, perform addressing, and select memory cells. At this time, when the address data changes, a phenomenon in which incorrect data is temporarily output, that is, a hazard may occur.

Specifically, a sense amplifier determines whether data in a memory cell selected by a decoder is "1" or "0", and an output circuit outputs the data to the outside.
However, in such a circuit, the potential of the column line to which the memory cell is connected is generally set to "1" or "0".
It determines this and outputs it as is as the information stored in the memory cell. Therefore, when the output of the decoder changes, a situation occurs in which no memory cell is specified or two or more memory cells are selected at the same time. At this time, the potential of the column line becomes unstable, and as shown in FIG. 1A to D,
Sometimes different data may be output. In other words, as shown in Figures A and B, when moving from the ``1'' level to the ``0'' level, conversely, in the transition state from the ``0'' level to the ``1'' level, there is an instantaneous change that occurs once. This may generate ivy data. Also,
As shown in C and D of the same figure, from "1" to "1"
Alternatively, even when outputting data at the same logic level, such as from "0" to "0", different data may be instantaneously generated. Also,
Such a hazard may also occur if the substrate potential becomes unstable.

The present invention was made in view of the above circumstances, and provides a semiconductor memory that eliminates memory output hazards and reliably prevents malfunctions of external circuits connected to the memory output circuit. The purpose is to provide.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows its schematic configuration. In the figure, reference numeral 11 denotes a memory cell array, in which memory cells (for example, MS) are provided at each intersection of row lines Ro to Rn and column lines lo to lm arranged in a matrix. Row and column decoders 12 and 13 select this memory cell. The row decoder 12 specifies one of the row lines Ro to Rn using address data An to Ai supplied from a CPU (not shown) or the like. On the other hand, the column decoder 13 specifies one of the column designation lines Co to Cm. This column designation line
Co to Cm are entrenchment type MOSs, respectively.
Connected to the gates of transistors To~Tm. One side of the source/drain path of the transistors To to Tm is connected to the column lines lo to lm, respectively. The other side is commonly connected at the node S, and the column gate circuit 1 is connected to the transistors To to Tm.
4. Therefore, for example, the row line Ro
is specified and the column designation line Co is specified, the transistor To becomes conductive and the column line lo
The data stored in the memory cell MS located at the intersection of the row line Ro and the row line Ro will be guided to the node S. Then, the potential of this node S is supplied to the output circuit 15 as an output signal H from the column gate circuit 14. This output circuit 15 detects the potential at the node S, performs waveform shaping, amplification, etc., and outputs the data content of the selected memory cell as an output signal D from the output terminal OUT. This output circuit 15 further includes a pulse generation circuit 16 that generates pulses in response to changes in address data Ao to Ai.
A signal B from is supplied.

The output circuit 15 is configured as shown in FIG. 3, for example. That is, the output signal H from the column gate circuit 14 is supplied to the sense amplifier 151. This sense amplifier 151 is connected to the inverter 15
2 and depletion type transistor 153
It consists of Note that the inverter 152
has depletion type and enhancement type transistors connected in series between power supply Vc and ground. The output signal of the sense amplifier 151 is supplied to an inverter 154. The output signal from inverter 154 is supplied to enhancement type transistor 155 and inverter 156. The transistor 155
The source is connected to ground, and the output signal B from the pulse generating circuit 16 is supplied to the gate. That is, when the signal B is at the "1" level, the transistor 155 becomes conductive;
The output of the inverter 154 is forced to be near the ground potential, that is, to the "0" level. Inverter 1
The output signal of 56 is supplied to the gate of a depletion transistor 159 of a circuit 158 having an inverter 157 and an enable terminal. This circuit 158 has a configuration in which an enhancement type transistor 160, a deceleration type transistor 159, and an enhancement type transistor 161 are connected in series between the power supply Vc and the ground. At the gate of the transistor 160,
A chip select signal CS that is at the "1" level is supplied when this semiconductor memory is selected. Further, the output signal of the inverter 157 is supplied to the gate of the transistor 161. That is, this circuit 158 is activated when the chip select signal is at the "1" level.
The output signal of the inverter 157 is inverted and output. Furthermore, the output signals of inverters 156 and 157 are transmitted to circuit 16 configured similarly to circuit 158.
When the chip selection signal CS is "1", the output signal of the inverter 156 is inverted by the circuit 162 and outputted. And circuit 1
The output signals P and Q of 58 and 162 are respectively supplied to the drains of enhancement type transistors 163 and 164 and to the gates of enhancement type transistors 165 and 166. The sources of the transistors 163 and 164 are connected to ground, and the chip selection signal is connected to the gate.
An inverted signal CS of CS is supplied. Further, the transistors 165 and 166 are connected in series between the power supply Vc and the ground, and the potential at the connection point is outputted as an output signal D from the terminal OUT.

That is, when the chip select signal CS is "0", the signal CS becomes "1", transistors 163 and 164 are rendered conductive, and the gates of output buffer transistors 165 and 166 are both at the "0" level. , transistor 165,
166 is in a non-conducting state and the output signal D is in a floating state. In other words, this memory is in a non-selected state.

Further, when the chip select signal CS is "1", the circuits 158 and 162 are in an operating state, and their output signals P and T cause the transistors 165 and 16 to
6 is on/off controlled, and the level of the output signal D is determined. In other words, this memory is in a selected state.

That is, the output circuit 15 configured in this way
, when the signal CS is in the selected state of "1" and the output signal H from the column gate circuit 14, that is, the storage information of the selected memory cell is, for example, "0", the output of the sense amplifier 151 is "0". ” as,
The signal is input to the inverter 154. The output of this inverter 154 becomes "1" when the signal B from the pulse generating circuit 16 is "0". Then, the inverters 156, 157 and the circuit 158 invert each signal, and the signal P becomes "0", turning off the transistor 165. Further, the output of the inverter 154 which is at the "1" level is the output of the inverter 1
56 and circuit 162, the signal Q becomes "1" and turns on the transistor 166. Therefore, the output signal D becomes "0".

Here, as shown in Figure 4, the address data
When Ao to Ai changes and, for example, another memory cell whose memory content is "0" is selected, the signal B from the pulse generation circuit 16 changes within a certain period, for example,
The signal H remains at the "1" level until the information of the selected memory cell appears. Therefore, the output of the inverter 154 is forced to the "0" level,
Contrary to the case where the output of the inverter 154 was at the "1" level during that period, the signal P becomes "1".
The signal Q becomes "0" and the output signal D becomes "1". Therefore, even if a hazard occurs in the signal H, the output signal D is forced to the "1" level by the pulse width of the signal B which is at the "1" level. Therefore, no hazard occurs in the signal D. Similarly, even if a hazard appears when signal H changes from "0" to "1" in response to changes in address data Ao to Ai, signal B forces signal D to "1". level, so no hazard will occur. Further, similarly, when the signal H changes from "1" to "1", no hazard occurs in the output signal D.

In this way, since the level of the output signal D is forced to the "1" level when the address changes, no hazard occurs in the signal D. As a result, the signal D
Once becomes the "1" level, the information stored in the memory cell is output.

Also, by doing this, when the address input changes, the output terminal OUT becomes "1", so there is no need to suddenly change the output to "1", and the data of the selected memory cell is output as a signal H. It suffices if it becomes ``1'' by the time it is released.

Generally, the current that the output terminal of a semiconductor memory should supply is determined. This output current is about 2.1mA when the output terminal is 0.45V when "0" is output, while it is 400μ when the output is 2.4V when "1" is output.
A grade is sufficient. This means that one
It is assumed that TTL is connected.

Therefore, the transistor 165 should be sufficiently smaller than the transistor 166 considering only the current supply. However, conventionally, this transistor 165 is made of a transistor with almost the same dimensions as 166. This is because a large capacitance of 150 PF is usually added to this output terminal, so when the output is set to "1" or "0", this capacitance must be charged and discharged.
Therefore, if the transistor 165 in the output stage also does not have sufficient current supply capability, it will take time for the output to reach the "1" level, resulting in a slow reading speed of the memory. For this reason, since it is desired to quickly bring the output to the "1" level, the dimensions of this transistor 165 are also made large.

However, if the arrangement is as shown in FIG. 3, when the address input changes, the output will be set to the "1" level once. Now, assume that the selected memory cell stores information to be output at the "1" level. Signal B becomes “1” as address changes
The output of the inverter 154 is forced to the "0" level, and the output D becomes "1". Then, the signal H becomes the memory cell information "1",
Even if signal B becomes “0”, inverter 1
The output of 54 remains at "0" because the signal H is "1". Therefore, the output D remains at "1". In other words, the output D can be brought to the "1" level immediately after the address input changes, and there is no need to suddenly bring it to the "1" level after detecting the information in the memory cell as in the past. As mentioned above, the transistor 165 can be made so that the output terminal has a current capacity of 400 μA at 2.4 V, and the size of this transistor can be made smaller than before.
Also, if this transistor 165 becomes smaller,
The circuit 158 is also reduced in size, and the output circuit of this semiconductor memory itself can be made smaller.

Next, a specific example of the pulse generating circuit 16 is shown in FIG. The pulse generation circuit 16 includes generation circuits 17o to 17i to which address data Ao to Ai are respectively supplied. The generation circuits 17o-17i generate pulse signals Bo-Bi, respectively, when the logic level of the corresponding address data Ao-Ai changes. this signal
Bo to Bi are supplied to a NOR circuit 18 and output as a signal B, and further output as a signal B via an inverter 19. The generating circuits 17o to 17i are constructed in the same way, and, for example, the generating circuit 17o is shown in FIG. Address data Ao is inverter 2
0, 21, 22, and 23, and the output signal Ao' of the inverter 23 is inverted by the transistor 24.
source. Also, address data Ao
are inverted by inverters 20, 21, and 25, respectively, and the output signal A'o of inverter 25 is supplied to the source of transistor 26. Also, the signal
A'o is inverted by inverter 27, delayed by transistor 28 and capacitor 29, and supplied to inverter 30. Then, it is further inverted by the inverter 30, further delayed by the transistor 31 and the capacitor 32, and the inverter 3
3. The output signal x of the inverter 33 is supplied to the gate of the transistor 26 and also to the inverter 34. The output signal y of the inverter 34 is supplied to the gate of the transistor 24, the drains of the transistor 24 and the transistor 26 are connected, and the potential at the connection point is output as the signal Bo.

In the pulse generating circuit 16 configured as described above, when the address data Ao changes from "0" to "1" to "0", for example, as shown in FIG. 7, the signal A'o also changes in the same way. The level changes from "0" to "1" to "0". Further, the signal A'o is an inverted version of the signal Ao. Signal x is transmitted through transistor 28, capacitor 29 and transistor 31, capacitor 32.
Therefore, it is a delayed version of the signal A′o. Furthermore, the signal y is an inverted version of the signal x. Since the transistor 24 is in the on state while the signal y is at the "1" level, the logic level state of the signal A'o is output as the signal Bo. Furthermore, since the transistor 26 is in the on state while the signal x is at the "1" level, the logic level state of the signal A'o is output as the signal Bo. Therefore, as shown in FIG. 7, the signal Bo becomes "1" by the time that the signal A'o is delayed by the transistor 28, the capacitor 29, the transistor 31, and the capacitor 32.
level. That is, when the address data Ao changes, the signal Bo remains at the "1" level for a certain period of time BT, and a pulse is generated by the twist. Then, the signal B is output as an inverted form of the signal Bo, and the signal B is further inverted. Similarly, address data
A pulse is also generated as signal B when A ₁ to A _i changes.

FIG. 8 shows another application example of the output circuit 15 shown in FIG. , an enhancement type transistor 155 whose gate is supplied with the signal B from the pulse generating circuit 16 is provided for the output of the inverter 154 as shown by the broken line in FIG. However, transistor 155
A transistor similar to the above may be provided, such as a transistor 155a for the output of the sense amplifier 151, or a transistor 155b for the output of the inverter 156. In this case, while the pulse signal B is at the "1" level, the output signal D is forced to be at the "0" level,
Thereafter, the data of the selected memory cell is output.

That is, a transistor similar to the transistor 155 may be provided anywhere on the transmission line up to outputting the signal from the column gate circuit 14 to the output terminal OUT. Further, although the transistor 155 is made conductive and connected to the ground when the signal B is "1", it may be connected to the power supply Vc.

FIG. 9 shows another embodiment of the output circuit 15, in which the signal from the sense amplifier is supplied to the source of the enhancement type transistor 40. A signal B from the pulse generation circuit 16 is supplied to the gate of this transistor 40. Further, this signal B is inverted by an inverter 41,
Supplied to the gate of enhancement type transistor 42. When the signal B is at the "1" level, the transistor 40 is turned on, and the signals from the sense amplifier are inverted by inverters 43 and 44, respectively. Further, when the signal B is at the "0" level, the transistor 42 is turned on, and a feedback path is formed between the output of the inverter 44, the drain of the transistor 40, and the input of the inverter 43. Therefore, the inverter 44
The previous output in is held as is. That is, the portion surrounded by the dashed line in the figure forms a type of latch circuit (memory circuit) 39.

The output of the inverter 44 is inverted by an inverter 45 and supplied to a circuit 46 having an enable terminal. This circuit 46 inverts the output of the inverter 45 when the chip selection signal CS is at the "1" level, and supplies the output to the gate of the output buffer transistor 47. Also, inverter 4
The output of 4 is fed to circuit 48 and outputs a chip select signal.
When SC is at the "1" level, it is inverted and supplied to the gate of the output buffer transistor 49. Transistors 47 and 49 are connected in series between a power supply Vc and ground, and the potential at the connection point is outputted as an output signal D.
As such, it is output from the output terminal OUT'.

That is, in such an output circuit, when the chip selection signal CS is at the "0" level, that is,
When the inverted signal CS is at the "1" level, the transistors 50 and 51 are turned on, the gates of the output buffer transistors 47 and 49 are both at the "0" level, and the output is in a floating state, making it unselected. It is in a state of

Furthermore, when the chip selection signal CS is at the "1" level, as shown in FIG. Consider the case where "0" and "0" are output. At this time, assume that a hazard occurs at the change in data from the sense amplifier as shown in the figure. On the other hand, the signal B from the pulse generating circuit 16 is normally at the "1" level, and the output circuit outputs a signal having the same level as the data from the sense amplifier as the output signal D. For example, if the data from the sense amplifier is at the "1" level, the output of the inverter 44 is "1", the output of the circuit 46 is also "1", and the output of the circuit 48 is "0", so the output Signal D becomes "1". At this time,
When address data Ao to Ai change and signal B becomes "0" level, output B of inverter 41
becomes "1", and the transistor 42 is turned on. Therefore, as mentioned above, the inverter 4
A feedback path is formed between the output of transistor 40 and the input of drain inverter 43 of transistor 40, and the output of inverter 44 is held at "1". Then, when the signal B returns to the "1" level, a signal having the same level as the data from the sense amplifier is output as the output signal D. That is,
When the address data Ao to Ai change, a new memory cell is selected, and the data of the new memory cell appears at the output of the sense amplifier, the signal B is set to "0" level for a certain period of time, and the data of the previous memory cell is Even if a hazard occurs in the output of the sense amplifier, no hazard will occur in the output signal D.

In this embodiment of the output circuit, the voltage waveforms of the signals B, B may be B', B' as shown in FIG. 10B. That is, after address data change, when the signal H is in a sufficiently stable state, the signal B' is set to the "1" level and the level of the signal H at that time is maintained and output, so no hazard occurs. signal like this
B' and B' can be easily generated from the pulse generating circuit 16 as described above.

Another embodiment of the pulse generation circuit for generating the signals B' and B' as described above is shown in FIG. Note that the same parts as in FIG. 2 are indicated with the same reference numerals.
This pulse generating circuit 61 detects a change in the potential level of the row lines Ro to Rn or the column designating lines Co to Cm and generates a pulse signal B'.

The potential of the column line Co is supplied to the drain of the enhancement type transistor ₆₂₀ , and is also supplied to the drain of the enhancement _type transistor 620 via the inverter ₆₃₀ .
is supplied to the gate. The above inverter 63
The output of ₀ is grounded via capacitor ₆₄₀ . The source of the transistor ₆₂₀ is connected to the drain of the enhancement type transistor ₆₅₀ at a node C'o. A signal B' is fed back into the gate of this transistor ₆₅₀ , and when this signal B' becomes "1", the node C'o is grounded. And that node C′o
The potential at is supplied to the NOR circuit 66.

Similarly, the potential of the column designation line C ₁ is supplied to the drain of the transistor 62 ₁ and also to the gate of the transistor 62 ₁ via the inverter 63 ₁ . The power of the inverter ₆₃₁ is grounded via the capacitor ₆₄₁ . The source of the transistor 62 ₁ is connected to the drain of the transistor 65 ₁ at a node C' ₁ . The gate of this transistor ₆₅₁ has a signal
When B' is input and reaches the "1" level as described above, the node _C'1 is set to the "0" level. This collocation point
The potential at _C'1 is supplied to the NOR circuit 66.

_{The column} designation lines C ₂ , _{C 3 .}

On the other hand, for the row lines R _{0 ,} R _{1 ,} ... _{R o ,} the respective nodes are
The potentials at R′ ₀ , R′ ₁ , . . . R′ _o are supplied to the NOR circuit 67 .

Output signals F ₁ and F ₂ from the NOR circuits 66 and 67 are supplied to inverters 68 and 69, respectively. The outputs of the inverters 68 and 69 are passed through integration circuits 70 and 71, respectively, as signals F ₃ and F ₄ .
The signal is supplied to the NOR circuit 72. And Noah circuit 7
2's output signal B' is inverted by an inverter 73 and supplied to the output circuit 15 as a signal B',
It is supplied to NOR circuits 74 and 75. This Noah circuit 7
The outputs of NOR circuits 4 and 75 are supplied to NOR circuits 66 and 67, respectively, and output signals F ₁ and F ₂ of NOR circuits 66 and 67 are input to NOR circuits 74 and 75, respectively.

That is, in the pulse generating circuit 61 configured in this way, as shown in FIG. 12, the address data Ao to Ai change, and for example, the potential of the column line Co changes from the "0" level to the "1" level. Suppose that it changes to . At this time, the output of the inverter ₆₃₀ is at the "0" level, but the capacitor ₆₄₀ keeps the transistor ₆₂₀ on. Therefore, the potential at the node C'o also rises from "0" to "1" as shown in FIG. Conversely, the output signal F ₁ of the NOR circuit 66 changes from the "1" level to the "0" level. And this signal F ₁
is inverted by the inverter 68, and the output signal _F3 of the integrating circuit 70 gradually rises to "1" as shown in FIG. Therefore, when the NOR circuit 72 determines that the signal _F3 is "1",
The signal B' is set to "0" level. i.e. the signal
Let B' be the "1" level. This signal B' that has reached the "1" level turns on the transistor ₆₅₀ , and the node C'o becomes the "0" level again.
As a result, the signal F ₁ becomes "1" level,
Signal B' becomes "0" level. Therefore, the signal
Period during which B′ is at “1” level (pulse width BT′)
is determined by the values of the resistor and capacitor that constitute the integrating circuit 70. Similarly, when the potential level of any of the row lines Ro to Rn changes, the signal F ₂ changes from "1" to "0" level, and the signal F ₄ gradually changes to "1" level by the integrating circuit 71. . As a result, the signal B' becomes the "1" level, and a pulse signal is generated in the same manner as described above.

Note that in the pulse generating circuit 61, the NOR circuits 74 and 75 do not need to be provided. Also,
When the transistors 64 ₀ , 64 ₁ ... are in the off state,
Since the nodes C′ ₀ , C′ ₁ ... are in a floating state, the transistors whose sources are grounded and gates are turned on are called transistors 65 ₀ , 65 _{1 .}
It may also be provided in parallel. At this time, it is preferable to use a transistor with a low resistance value that does not prevent the nodes C' ₀ , C' ₁ , . . . from going from the "0" level to the "1" level.

Further, the optimal timing for the rise of the signal B' is to start when the data of the selected memory cell is transmitted as the signal H to the output circuit 15.

As described above, according to the present invention, after the address input changes, the data of the selected memory cell is output after outputting data at a specific level, which eliminates the hazard of memory output and connects it to the output circuit. Accordingly, it is possible to provide a semiconductor memory that can reliably prevent malfunctions of circuits that may occur.

[Brief explanation of the drawing]

FIGS. 1A, B, C, and D are diagrams for explaining hazards in conventional memory output, FIG. 2 is a diagram showing the configuration of a semiconductor memory according to an embodiment of the present invention, and FIG. 4 is a timing chart explaining the operation of the output circuit; FIG. 5 is a diagram showing the configuration of the pulse generating circuit; FIG. 6 is a circuit diagram of the generating circuit in the pulse generating circuit; FIG. FIG. 7 is a timing chart explaining the operation of the above generation circuit, FIG. 8 is a circuit diagram explaining an application example of the above output circuit, and FIG. 9 is a circuit showing another embodiment of the output circuit in the above pre-semiconductor memory. 10A and 10B are timing charts explaining the operation of the output circuit in FIG.
FIG. 1 is a circuit configuration diagram showing another embodiment of the pulse generation circuit in the semiconductor memory, and FIG.
2 is a timing chart illustrating the operation of the pulse generation circuit in FIG. 1. FIG. 11... Memory cell eye, 12... Row decoder, 13... Column decoder, 14... Column gate circuit, 15... Output circuit, 16... Pulse generation circuit, 61... Pulse generation circuit.

Claims (1)

[Claims] 1 A memory cell selected by address input, an output circuit that outputs data of the selected memory cell, a pulse generation circuit that detects address change and generates a pulse signal, and is provided in the output circuit, The device is characterized by comprising level setting means that uses the pulse signal from the pulse generating circuit to determine the output state of the output circuit so as not to output an output for a predetermined period after the address changes. semiconductor memory.