JPS61187100U - - Google Patents
Info
- Publication number
- JPS61187100U JPS61187100U JP7135385U JP7135385U JPS61187100U JP S61187100 U JPS61187100 U JP S61187100U JP 7135385 U JP7135385 U JP 7135385U JP 7135385 U JP7135385 U JP 7135385U JP S61187100 U JPS61187100 U JP S61187100U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- refresh address
- frequency divider
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図および第３図は夫々本考案の実施例を示
す回路図である。第２図は第１図に示したＣＰＵ
１０のＭ１サイクルのタイミングチヤートである
。
1 and 3 are circuit diagrams showing embodiments of the present invention, respectively. Figure 2 shows the CPU shown in Figure 1.
This is a timing chart of 10 M1 cycles.
Claims (1)
正の整数）構成のリフレツシユアドレス信号を受
け、該信号に応答して２Ｎサイクルカウントする
カウンタ回路と、該カウンタ回路の出力を分周す
る分周回路とを有し、該分周回路から前記リフレ
ツシユアドレス信号の最上位に付加すべき信号を
得ることを特徴とするアドレス制御回路。 A counter circuit that receives a refresh address signal of N bits (N is a positive integer) as a refresh address and counts 2N cycles in response to the signal, and a frequency divider circuit that divides the output of the counter circuit. An address control circuit characterized in that the address control circuit has a frequency divider circuit and obtains a signal to be added to the most significant part of the refresh address signal from the frequency dividing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7135385U JPS61187100U (en) | 1985-05-14 | 1985-05-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7135385U JPS61187100U (en) | 1985-05-14 | 1985-05-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61187100U true JPS61187100U (en) | 1986-11-21 |
Family
ID=30608772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7135385U Pending JPS61187100U (en) | 1985-05-14 | 1985-05-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61187100U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223098A (en) * | 1984-04-18 | 1985-11-07 | Foster Denki Kk | Refresh circuit of dynamic random access memory |
-
1985
- 1985-05-14 JP JP7135385U patent/JPS61187100U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223098A (en) * | 1984-04-18 | 1985-11-07 | Foster Denki Kk | Refresh circuit of dynamic random access memory |
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