JPS61177187A - Pll synchronous monitoring apparatus - Google Patents

Abstract

PURPOSE:To confirm the locking state of a DC motor at high precision, by comparing voltage as the result of phase-comparing reference signal with rota tional output signal, and by driving a LED. CONSTITUTION:A PPL synchronous monitoring apparatus for confirming the locking state of a DC motor is organized with a phase comparator 1 comparing the phase difference between reference signal Ea and rotational output signal Er, a voltage comparator 2 with the compared output Ed for the first input and reference voltage ES1 for the second input, a voltage comparator 3 with reference voltage ES2 for the first input and said voltage Ed for the second input. NAND gates 4, 5, and the series circuit of a LED 7 and a resistance 8. In this manner, for example, when the phase in the rotational output signal Er is passed by 1/2 cycle or more than in the reference signal Ea, then the output Ed of the phase comparator 1 corresponds to the output of pulse more positive than that on a reference level, and the operation of the first and the second comparators 2, 3 is turned to a level 0, and only during the term, the LED 7 is lit, and it can be known that PLL is getting out of a locking state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PLL synchronization monitoring device capable of detecting unlocking of a PLL when driving a DC motor using a PLL control method.

(Prior Art) An electronic copying machine exposes a charged drum to light in accordance with document information, and then forms a toner visible image on an electrostatic latent image formed on the drum surface. This is a device that transfers the image onto recording paper. In recent years, this type of electronic copying mode has been widely used for information copying in all fields of industry. Recent electronic copying machines are available on the market that not only automatically make one copy, but also have a zoom function for enlarging or reducing images.

This type of electronic copying machine uses a main motor for rotating a drum and an optical motor for operating an optical system. As the main motor, for example, an induction motor is used, and as the optical motor, for example, a DC motor is used. Recently, a PLL control method has been used as a drive method for a DC motor.

The PLL control method drives a DC motor with a clock pulse (reference signal), detects the actual rotational output signal of the rotating motor, and ensures that the reference signal and rotational output signal always have a constant phase relationship. It is something to control.

(Problems to be Solved by the Invention) When driving a DC motor using the PLL control method, if the reference signal and the rotation output signal are in a locked state, the DC motor is rotating at a constant speed. However, if the lock is released for some reason, the DC motor will no longer be able to rotate at a normal constant speed. As a result, the operation of the optical system becomes distorted, making it impossible to obtain a high-quality copy image. Conventionally, the phase relationship between the reference signal and the rotational output signal could only be confirmed by observing the waveform with an oscilloscope. Therefore,
Without an oscilloscope, it was impossible to confirm whether the lock was released or not, which was very inconvenient.

The present invention has been made in view of the above points, and an object of the present invention is to provide a PLL control system that can check the locked state of a DC motor driven by a PLL control method.
The objective is to realize a synchronous monitoring device.

(Means for Solving the Interval Vertex) The present invention, which solves the above-mentioned problems, compares the phases of the reference signal and the rotation output signal of the DC motor when driving the DC motor using the PLL control method, and The present invention is characterized in that the phase comparison result and the reference voltage are compared, and the lamp is lit by an AND signal between the voltage comparison result and the reference signal.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an electrical circuit diagram showing one embodiment of the present invention.

In the figure, 1 is a phase comparator that compares the phase difference between the reference signal Ea and the rotational output signal Er, 2 is the phase comparison output Ed of the phase comparator 1 as the first input, and the reference voltage ES+ as the second input.
A voltage comparator 3 receives the jiiQJ voltage ES voltage at its S2 input, and receives the output Ed of the phase comparator 1 at its second input. 4 is the output E of voltage comparator 2
A Nant gate 5 receives Ct as one input and a reference voltage QEa as the other input, 5 is a signal Ea obtained by inverting the reference signal Ea with an inverter 6, with the output EC2 of the voltage comparator 3 as one input.
It is a Nantes gate that receives the other input.

The outputs of these Nant gates 4.5 are connected in common, and a series circuit of an LED 7 and a resistor is connected to this common connection point. At the other end of LED7? U source voltage VCC is connected. The output of the Nandgate 4°5 is an oven collector. Therefore, a series circuit of an LED 7 and a resistor 8 is connected to the output of the Nant gate 4.5, forming a so-called wired-OR circuit. The operation of the circuit configured as described above will be explained below with reference to a timing chart.

First, the operation in the locked state will be explained. Second
The figure is a timing chart showing the operation of each part in the locked state. In the figure, (a) is a duty ratio of 50
(b) is the rotational output signal Er, (c) is the output of the phase comparator 1, (d) is the output EC+ of the first voltage comparator 2, and (e) is the output of the second voltage comparator 2. The output EC2 of the voltage comparator 3, (to) the output Ea of the inverter 6, (g)
is the output EOt of the first Nant gate 4, and (H) is the output of the second Nant gate 4.
() indicates the output EO2 of the Nantes gate 5, and () indicates the lighting state of the LED 7, respectively. Regarding the lighting state of the LED 7, the "1" level indicates the lighting state, and the "0" level indicates the lighting state.

The phase comparator 1 receives a reference signal E as shown in FIG.
In response to the rotation output signal Er as shown in FIG. 1A and FIG. Phase comparator 1 generates two human input signals Ea.

The reference point for comparing Er is the rise of the reference voltage @Ea. When the rising edge of the rotational output signal Er is seen than the rising edge of the reference signal Ea (A region 1iJ in the figure), Er is in a phase delayed state than Ea, and the rotational output signal Er is slower than the rising edge of the reference signal Ea. When the rise is early (region 8 in the figure), Er is in a state where the phase is ahead of Ea. The phase comparator 1 outputs a pulse having a width corresponding to the difference between the rising edges of Ea and Er. During the lagging phase, the phase comparator 1 outputs a pulse in the negative direction, and during the leading phase, the phase comparator 1 outputs a pulse in the positive direction.

The output lad of the phase comparator 1 is applied to the positive input of the first voltage comparator 2 and the negative input of the second voltage comparator 3. Here, the reference voltage ESt of the first voltage comparator 2 is set to the power supply voltage V
The reference voltage ES2 of the second voltage comparator 3 is set to be 315 times larger than CC, and the reference voltage ES2 of the second voltage comparator 3 is set to be 2775 times larger than the power supply voltage VCC. In the slow phase state shown in region A, the output of the phase comparator 1 is a negative direction pulse as shown in (c). Therefore, the input of the first voltage comparator 2 is ES 1 >
Since there is a relationship Ed, the output EC is ゛○゛ level as shown in (d). On the other hand, the second voltage comparator 3
Since the inputs of are in the relationship ES2>Ed, and ES2 is in the positive input, the output EC2 is at the ``1'' level as shown in (e).

That is, the output of the second voltage comparator 3 becomes a pulse as shown in (d).

The Nant gate 4 receives the reference signal Ea and the output of the first voltage comparator 2;/]ECt, but since EC+ is at the OII level, its output EO, is (T) regardless of the value of Ea.
On the other hand, the Nant gate 5 receives the inverted signal Ea of the reference signal Ea as shown in (v) and the output EC2 of the second voltage comparator 3, but ECz
When is at the “1” level, the inverted signal Ea is “0”0°0°
level, and its output EO2 is still at the "1" level as shown in (H). Therefore, since the outputs EOI and EO2 of the Nant gates 4 and 5 are both at the "1" level, the LED 7 is It does not light up as shown in (a).

Next, in the advanced phase state shown in region B, the phase comparator 1 outputs Ea', ! as shown in (c). : Outputs a positive direction pulse based on the difference in Er. Since the input of the first voltage comparator 2 has a relationship of Ed > ES 2, its output EC
+ becomes a pulse waveform as shown in (d). On the other hand, the second
The inputs of voltage comparator 3 have a relationship of Ed>ESz, and since ES2 is the positive input, its output EC2
is always at the ``0'' level as shown in (e).

The Nant gate 4 connects the reference signal Ea and the first voltage comparator 2.
However, when EC+ is at the '1' level, Ea is at the '0' level, so its output EOI is at the '1' level as shown in (g). 5 receives the reference signal Ea and the output of the second voltage comparator 3, but in the advanced phase state, EC'2 is always at O'' level. Therefore, the output E02 of the Nant gate 5 is always at the "1" level, regardless of the value of Ea, as shown in (h).

Therefore, in this case as well, the LED 7 will not light up. The operator can check this LED display to confirm that the PLL is in a locked state and that the DC motor is rotating normally. Thus, according to the present invention, the reference signal Ea
The phase relationship between rotation output signal Er and rotation output signal Er is a constant phase difference (1/2
(period), the LED 7 indicating the abnormal vJ operation state will not light up.

Next, between the reference signal [a and the rotation output signal Er, 1/2
The operation when a delay or advance exceeding a cycle occurs, that is, when the lock is released, will be explained.

FIG. 3 is a timing chart showing the operation of each part when the rotation output signal Er is delayed by 1/2 cycle or more with respect to the reference voltage @Ea. The waveforms (A) to (S) are the same as those in FIG.

When the rotational output signal Er lags the reference signal Ea by 1/2 period or more as shown in FIGS. 3(a) and (b), the phase comparator 1 outputs a comparison result signal as shown in Output Ed. The first and second voltage comparators 2.3 are each E
d and the reference voltage ES.

ES2 and outputs signals as shown in (D) and (E). That is, since Ed outputs a pulse in the negative direction than the reference level as shown in (c), Ed < ES
Therefore, the output of the first voltage comparator 2 is always at the OII level as shown in (d). On the other hand, the input of the second voltage comparator 3 has a relationship of Ed < ES 2 while Ed is falling in the negative direction, so its output EC2 is at the "1"level; otherwise, Ed > Since it becomes ES2, EC2 becomes "O" level. As a result, the output EC2 of the second comparator 3 becomes a pulse as shown in (e).

The Nant gate 4 outputs the output EC'S of the first voltage comparator 2.
and receives the reference signal Ea, but since Ect is always at the "O'° level, its output EO, is always at the voltage level as shown in (g). On the other hand, the Nant gate 5 is connected to the second voltage comparator. The output EC2 of 3 receives the inverted signal Ea of the quasi-signal.As shown in (E) and (F), there is a state in which both the two inputs are at 1° level, so only during this period does the Nantes gate 5 The output EO2 is 0 as shown in (g).
As a result, the LED 7 lights up as shown in (S) only while EC2 is at O'' level, notifying the operator that the PLL is unlocked.

Next, the rotation output signal Er is 1.7 higher than the reference signal lea.
The operation when the phase is ahead by two cycles or more will be explained. FIG. 4 is a timing chart showing the operation of each part at this time. The waveforms (A) to (S) are the same as those in FIG. In this case, the output Ed of the phase comparator 1 is M
Corresponding to outputting a pulse in the positive direction than the reference signal, the operations of the first and second comparators 2.3 are reversed to those in FIG. 3. That is, as shown in (e), EC2 is always at the "O" level, and EC+ is a pulse as shown in (d).Then, the Nant gate 4 is connected to the reference signal Ea and "O" level.
Only when both C1 are at the "1" level, a pulse-like signal of the "0" level as shown in FIG. The operator can know that the PLL is unlocked by observing the lighting state of this LED.

In the above description, an example has been described in which one LED is lit to notify the operator of malfunction when unlocking either slow phase or fast phase lock, but the present invention does not need to be limited to this. Nantes Gate 4.5 as shown in Figure 5
It is also possible to separately connect an LED to each of the outputs, and to light up a separate LED for each phase delay abnormality or phase advance abnormality.

Note that the lighting indicator lamp is not limited to an LED, and may be any lighting light source.

In the above description, a case has been described in which the LED blinks to notify the operator when the lock is released, but it is difficult to tell that the LED is lit by blinking. This is especially true when the light is blinking repeatedly at high speed. In order to eliminate such a problem, the configuration may be such that when either one of the Nant gates 4, 5 reaches the "0" level, the "O" level state is latched so that the LED is always lit.

Furthermore, in the above explanation, the duty ratio of the reference signal [a is set to 50
The normality/abnormality of the PLL operation is determined based on that half cycle as a reference, but if the reference signal Ea is multiplied by 2 or 4 times and used as a new reference signal, 1, z 4 of the motor clock PLLI based on period, 1/8 period
! It is possible to determine whether the IJ work is normal or abnormal, and it is possible to perform a determination operation with higher accuracy.

(Effects of the Invention) As explained in detail above, according to the present invention, the phase comparison between the reference signal and the rotation output signal is performed, the voltage comparison is performed using the result, and the voltage-voltage comparator is operated using the result. The voltage comparator output is input to the gate circuit, and the gate circuit outputs the LED.
By driving, it is possible to confirm the locked state of the DC motor driven by the PLL control method, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing one embodiment of the present invention, FIGS. 2 to 4 are timing charts showing the operation of each part, and FIG.
The figure is an electrical circuit diagram showing another embodiment of the present invention. 1... Phase comparator 2, 3... Voltage comparator 4
．． 5...Nant Gate 6...Inverter 7.7'
...LED 8.8-...Resistance patent applicant
Representative of Konishiroku Photo Industry Co., Ltd. Patent attorney Fuji Yujima 1 person outside the jurisdiction

Claims (1)

[Claims] When driving a DC motor using the PLL control method, the reference signal and the rotation output signal of the DC motor are phase-compared, the phase comparison result and the reference voltage are compared in voltage, and the voltage comparison result and the reference signal are compared. A PL characterized in that the lamp is configured to be lit by an AND signal.
L synchronization monitoring device.