JPS61174768A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61174768A
JPS61174768A JP1588185A JP1588185A JPS61174768A JP S61174768 A JPS61174768 A JP S61174768A JP 1588185 A JP1588185 A JP 1588185A JP 1588185 A JP1588185 A JP 1588185A JP S61174768 A JPS61174768 A JP S61174768A
Authority
JP
Japan
Prior art keywords
metal silicide
layer
electrode
thickness
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1588185A
Other languages
Japanese (ja)
Other versions
JPH0533544B2 (en
Inventor
Isao Kano
鹿野 功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1588185A priority Critical patent/JPS61174768A/en
Publication of JPS61174768A publication Critical patent/JPS61174768A/en
Publication of JPH0533544B2 publication Critical patent/JPH0533544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Abstract

PURPOSE:To prevent breakdown of a P-N junction, which is formed in a shallow depth, by making an electrode wiring layer of a metal silicide at a part of an electrode taking out part thinner than the other part. CONSTITUTION:Holes 13 are provided in an SiO2 film 12 as specified, and electrodes and wirings are formed by poly Si. Then, a part of the electrode is coated by SiO2. Pt is deposited on the entire surface, and heat treatment is performed. Pt silicide having a specified thickness is formed on the surface of the poly Si. The non-reacted Pt and the SiO2 mask are removed. The Pt is deposited again on the entire surface so that it is thinner than the first time. Heat treatment is performed. The Pt silicide is formed at the electrode part, which is masked at first. In the metal silicide layer, the resistance of the layer is decreased in inversely proportional to the thickness. The P-N junction of a semiconductor is broken at a certain thickness or more. In this constitution, however, since the metal silicide can be formed in a desired thickness, the breakdown of the P-N junction is prevented, and the device having low layer resistance is obtained at a high yield rate.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は金属シリサイド電極配線層を有する半導体装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a metal silicide electrode wiring layer.

〔従来の技術〕[Conventional technology]

従来半導体装置において、金属シリサイド電極配線とし
ては、白金シリサイド、チタンシリサイド、モリブデン
シリサイド等の高融点金属シリサイドが、半導体基板よ
りの電極引き出しや、SBDコンタクト、素子間の相互
配線として使用されてきた。
Conventionally, in semiconductor devices, high melting point metal silicides such as platinum silicide, titanium silicide, and molybdenum silicide have been used as metal silicide electrode wiring for leading out electrodes from semiconductor substrates, SBD contacts, and interconnections between elements.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の金属シリサイド電極配線層は、素子間の相互配線
部分においては配線の層抵抗を小さくすることが要求さ
れる0層抵抗を下げるためには当該金属シリサイド層を
厚く形成するとよいが、従来方法によると上記金属シリ
サイド層を厚く形成すると半導体基板の電極引き出し部
分の金属シリサイドも同様に厚く形成されるため、半導
体基板に浅く設けられたPN接合を破壊してしまうとい
う欠点があった。特にバイポーラ型の集積回路において
、エミッタ電極引き出しを金属シリサイドを用いて行う
場合には、金属シリサイド層を厚くすると、エミッタe
ベース接合を破壊してしまうため、金属シリサイドの厚
さは前記接合を破壊しない程度の厚さに制限する必要が
あった。
The above-mentioned metal silicide electrode wiring layer is preferably formed thickly in order to lower the 0 layer resistance, which is required to reduce the layer resistance of the wiring in the interconnection portion between elements, but conventional methods According to the above, if the metal silicide layer is formed thickly, the metal silicide at the electrode extension portion of the semiconductor substrate is also formed thickly, which has the disadvantage of destroying the PN junction formed shallowly in the semiconductor substrate. Particularly in bipolar integrated circuits, when drawing out the emitter electrode using metal silicide, if the metal silicide layer is made thicker, the emitter e
Since this would destroy the base bond, it was necessary to limit the thickness of the metal silicide to a thickness that would not destroy the bond.

本発明の目的は金属シリサイドの厚さを、上述の要求に
合うごとくした半導体装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the thickness of metal silicide meets the above-mentioned requirements.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の構成は、金属シリサイド電極配線層を有する半
導体装置において、電極引き出し部分の金属シリサイド
層の少なくとも一部分の厚さが、他の部分の金属シリサ
イド層より薄いことを特徴とする半導体装置である。
The structure of the present invention is a semiconductor device having a metal silicide electrode wiring layer, characterized in that the thickness of at least a portion of the metal silicide layer in the electrode extension portion is thinner than that of the metal silicide layer in other portions. .

次に本発明を図面を用いて説明する。Next, the present invention will be explained using the drawings.

第1図は本発明の一実施例の断面図であり、第2図は従
来構造の一例を示す断面図である0図においては1本発
明の説明に不要な部分は省略しである。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional structure. In FIG. 0, parts unnecessary for explaining the present invention are omitted.

従来方法においては半導体基板17上に常法により絶縁
膜12および素子分離用絶縁膜11を設け、絶縁膜12
の1部を開孔してコンタクト孔13を設け、さらに金属
シリサイド配線および金属シリサイド電極等を設けるた
めにポリシリコンパターン16を形成し1次いで例えば
白金を全面に被着させて熱処理を行い、ポリシリコンの
表面に金属シリサイド層を形成させていた。したがって
金属シリサイド電極部分24と、金属シリサイド配線部
分25の金属シリサイド層の厚さは同等である0本出願
人らの実験によれば、金属シリサイド層の厚さに反比例
して金属シリサイド層の層抵抗は低下するが、金属シリ
サイド層の厚さがある厚さ以上になると半導体基板に設
けられたPN接合を破壊してしまうことが判明している
In the conventional method, the insulating film 12 and the element isolation insulating film 11 are provided on the semiconductor substrate 17 by a conventional method, and the insulating film 12 is
A contact hole 13 is formed by opening a part of the contact hole 13, and a polysilicon pattern 16 is formed in order to provide metal silicide wiring, metal silicide electrodes, etc. Next, for example, platinum is deposited on the entire surface and heat treated to form a polysilicon pattern 16. A metal silicide layer was formed on the surface of silicon. Therefore, the thickness of the metal silicide layer in the metal silicide electrode portion 24 and the metal silicide wiring portion 25 are the same.According to experiments conducted by the present applicant, the thickness of the metal silicide layer is inversely proportional to the thickness of the metal silicide layer. Although the resistance decreases, it has been found that if the thickness of the metal silicide layer exceeds a certain thickness, the PN junction provided in the semiconductor substrate will be destroyed.

本発明の半導体装置は第1図に示すごとく金属シリサイ
ド電極部分14のシリサイドの厚さは薄く保ちながら層
抵抗を低くすべき例えば金属シリサイド配線部分15の
シリサイド層の厚さを厚くした半導体装置である。水装
置は以下のようにして製造される。先ず従来方法と同様
に半導体基板17上に絶縁膜 (SiO2) 12、素
子分離用絶縁膜11を設け、コンタクト孔13を開孔し
、全面にポリシリコン層をLPCVD法により形成した
のち、配線および電極を形成するためパターニングする
0次に少なくとも電極部分の一部を例えば5i02でマ
スクした状態で金属シリサイドを生成する金属例えば白
金を全面に被着し、熱処理を行い、マスクされた部分以
外のポリシリコン表面に一定の厚さの白金シリサイドを
生成させる。その後不要な未反応の白金およびマスクを
除去し、最初に被着した白金よりも薄い膜厚の白金を全
面に再び被着して熱処理を行い、最初にマスクされてい
て白金シリサイドが生成しなかった電極部分にも白金シ
リサイドを生成させる。また他の方法として、前述のパ
ターニングしたポリシリコン層の全面に白金を厚めに被
着し、少なくとも電極部分の一部の白金をスパッタエツ
チングにより薄くした後熱処理を行い、白金シリサイド
を生成させる。
As shown in FIG. 1, the semiconductor device of the present invention is a semiconductor device in which the thickness of the silicide in the metal silicide electrode portion 14 is kept thin and the layer resistance is reduced, for example, the silicide layer in the metal silicide wiring portion 15 is thickened. be. The water device is manufactured as follows. First, as in the conventional method, an insulating film (SiO2) 12 and an insulating film 11 for element isolation are provided on a semiconductor substrate 17, a contact hole 13 is opened, and a polysilicon layer is formed on the entire surface by the LPCVD method. After patterning to form an electrode, at least a part of the electrode part is masked with, for example, 5i02, and a metal that generates metal silicide, such as platinum, is deposited on the entire surface, heat treatment is performed, and the polygon is removed from the masked part. Platinum silicide of a certain thickness is generated on the silicon surface. After that, unnecessary unreacted platinum and the mask are removed, and a thinner layer of platinum than the initially deposited platinum is re-deposited over the entire surface and heat treated. Platinum silicide is also generated on the electrode parts. Another method is to apply a thick layer of platinum to the entire surface of the patterned polysilicon layer, thin the platinum in at least a portion of the electrode portion by sputter etching, and then perform heat treatment to generate platinum silicide.

以上の方法により、電極部分の金属シリサイド層および
他の部分例えば配線部分の金属シリサイド層の厚さをそ
れぞれ所望の厚さに形成することができることは明らか
である。
It is clear that by the above method, the metal silicide layer in the electrode portion and the metal silicide layer in other portions, such as the wiring portion, can be formed to have desired thicknesses.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、電極引き出し部分の金属シリサイ
ドの厚さを薄くし、他の部分例えば配線部分の金属シリ
サイドの厚さを厚くすることにより、高歩留りの、低層
抵抗をもった半導体装置を得ることができる。
As explained above, by reducing the thickness of the metal silicide in the electrode extraction portion and increasing the thickness of the metal silicide in other portions, such as the wiring portion, a semiconductor device with high yield and low layer resistance can be obtained. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体装置の断面図であり、第2図は
従来の半導体装置の断面図である。 11・・・素子分離用の絶縁膜 12・・・素子上の絶縁膜 13・・・素子上の絶縁膜に形成されたコンタクト孔1
4・・・電極部分に形成された金属シリサイド15・・
・金属シリサイド配線 16・・・電極配線用のポリシリコン 17・・・半導体基板 24・・・電極部分に形成された金属シリサイド25・
・・金属シリサイド配線
FIG. 1 is a sectional view of a semiconductor device of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 11... Insulating film for element isolation 12... Insulating film on the element 13... Contact hole 1 formed in the insulating film on the element
4...Metal silicide 15 formed on the electrode part...
・Metal silicide wiring 16...Polysilicon 17 for electrode wiring...Semiconductor substrate 24...Metal silicide 25 formed in the electrode part.
・・Metal silicide wiring

Claims (1)

【特許請求の範囲】[Claims] 金属シリサイド電極配線層を有する半導体装置において
、電極引き出し部分の金属シリサイド層の少なくとも一
部分の厚さが、他の部分の金属シリサイド層より薄いこ
とを特徴とする半導体装置。
1. A semiconductor device having a metal silicide electrode wiring layer, wherein at least a portion of the metal silicide layer in an electrode extension portion is thinner than other portions of the metal silicide layer.
JP1588185A 1985-01-30 1985-01-30 Semiconductor device Granted JPS61174768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1588185A JPS61174768A (en) 1985-01-30 1985-01-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1588185A JPS61174768A (en) 1985-01-30 1985-01-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61174768A true JPS61174768A (en) 1986-08-06
JPH0533544B2 JPH0533544B2 (en) 1993-05-19

Family

ID=11901129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1588185A Granted JPS61174768A (en) 1985-01-30 1985-01-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61174768A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51130169A (en) * 1975-05-07 1976-11-12 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51130169A (en) * 1975-05-07 1976-11-12 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0533544B2 (en) 1993-05-19

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