JPS6116552A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6116552A
JPS6116552A JP60134042A JP13404285A JPS6116552A JP S6116552 A JPS6116552 A JP S6116552A JP 60134042 A JP60134042 A JP 60134042A JP 13404285 A JP13404285 A JP 13404285A JP S6116552 A JPS6116552 A JP S6116552A
Authority
JP
Japan
Prior art keywords
bump
substrate
layer
solder
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60134042A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
宮本 圭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60134042A priority Critical patent/JPS6116552A/en
Publication of JPS6116552A publication Critical patent/JPS6116552A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To form a bump electrode easily at an arbitrary position on a semiconductor substrate, to which various elements are shaped, by constituting the titled integrated circuit device by the substrate, a wiring layer, an insulating film coating one main surface of the substrate except an electrode section, conductive layers of at least two layers, an uppermost layer thereof consists of a substance difficult to be wetted by solder, and a bump. CONSTITUTION:A hole is bored to a protective film 3 on an electrode section in a wiring layer 2 formed onto a substrate 1. Plating foundation layers composed of two layers are shaped onto the whole surface on the substrate. A plating layer 6 shaped according to a pattern so as to tie a desired arbitrary bump forming position on the substrate and the upper section of the electrode section in the wiring layer 2 is shaped. A solder bump 7 connected to the plating layer 6 is formed by using a photo-resist mask. Since the plating layer shaped into an uppermost layer is not wetted by solder, the solder bump does not extend over the substrate due to wetting. Lastly, the plating foundation layers are removed selectively through etching while employing the plating layer 6 and the solder bump 7 as masks.

Description

【発明の詳細な説明】 本発明は集積回路装置に関する。ここでは特に集積回路
装置等の基板上の所望とする任意の位置にはんだバンプ
電極を形成した集積回路装置について説明する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit devices. In particular, an integrated circuit device in which solder bump electrodes are formed at desired arbitrary positions on a substrate such as an integrated circuit device will be described.

はんだバンプ電極(通称CCB電極等)の形成された装
置としては、通常、配線完了後のウェハにさらにSin
、、5isN4あるいはポリイミド系ポリマー等からな
る絶縁性の保護膜を形成し、所要のバンプ形成位置にお
ける上記保護膜に穴あけを施し、上記穴あけ部に適宜の
バンプ下地膜を介してハンダバンプを形成した集積回路
装置が作られていた。
For devices in which solder bump electrodes (commonly known as CCB electrodes, etc.) are formed, the wafer is usually coated with additional solder bumps after wiring is completed.
,, an integrated structure in which an insulating protective film made of 5isN4 or polyimide polymer, etc. is formed, a hole is drilled in the protective film at a desired bump formation position, and a solder bump is formed in the hole through an appropriate bump base film. A circuit device was being created.

しかし、上述の如き従来の装置においては、バンプ位置
を基板上の任意の位置に形成するために多層配線構造と
せねばならず、それだけ多くの工数を要する欠点があっ
た。
However, in the conventional device as described above, a multilayer wiring structure must be used in order to form the bump position at an arbitrary position on the substrate, which has the drawback of requiring a correspondingly large number of man-hours.

尚、保護膜の穴あけ部に適宜のバンプ下地膜を介してハ
ンダバンプを形成した集積回路装置については、特開昭
54−113246号に記載されている。
An integrated circuit device in which solder bumps are formed in the perforated portions of the protective film via a suitable bump base film is described in Japanese Patent Laid-Open No. 113246/1983.

本発明は、配線層上の電極部に導通するはんだバンプ電
極を、基板上の任意の位置に容易に形成することができ
る新規な集積回路装置などを提供する目的でなされたも
のである。
The present invention has been made for the purpose of providing a novel integrated circuit device, etc., in which solder bump electrodes electrically connected to electrode portions on wiring layers can be easily formed at arbitrary positions on a substrate.

本発明の一実施例の概要は配線層の電極部上の保護膜に
穴あけを施した後、全面に例えばTiとCu等からなる
メッキ下地膜を形成し、その上に基板上の所望のバンプ
形成位置と、前記配線層の電極部とを結ぶようにパター
ン形成されたCrメッキ層を設け、次いで適宜のはんだ
下地層、例えばNi膜を介して上記C「メッキ層に接続
してはんだバンプを形成し、最後に上記Crメッキ層お
よびはんだバンプをマスクとし一残余のメッキ下地層を
エンチング除去することを特徴とするものである。
The outline of one embodiment of the present invention is that after drilling holes in the protective film on the electrode portion of the wiring layer, a plating base film made of, for example, Ti and Cu is formed on the entire surface, and desired bumps on the substrate are formed on the base film. A patterned Cr plating layer is provided to connect the formation position and the electrode part of the wiring layer, and then a solder bump is connected to the C plating layer through an appropriate solder base layer, for example, a Ni film. Finally, using the Cr plating layer and solder bumps as a mask, the remaining plating base layer is etched away.

第1図(a)乃至(e)は本発明の一実施態様を示す工
程毎の図である。
FIGS. 1(a) to 1(e) are diagrams showing each step of an embodiment of the present invention.

まず図(a)の如く、基板l上に形成された配線層2の
電極部上における保護膜3に穴あけを施す。
First, as shown in Figure (a), a hole is made in the protective film 3 on the electrode portion of the wiring layer 2 formed on the substrate l.

次に図の)の如<Ti膜4およびCu膜5の二層からな
るメッキ下地層を基板上の全面に形成する。
Next, a plating base layer consisting of two layers of a Ti film 4 and a Cu film 5 is formed on the entire surface of the substrate as shown in ).

次いで図(c)の如く、基板上の所望とする任意のバン
ブ形成位置と前記配線層2の電極部上とを結ぶようにパ
ターン形成されたCuメッキ層6を設げる。このために
は、Cr / Cu / T iの重ね膜を形成後、C
rをホトエツチングでバターニングすればよい。
Next, as shown in Figure (c), a patterned Cu plating layer 6 is provided so as to connect any desired bump formation position on the substrate with the electrode portion of the wiring layer 2. For this purpose, after forming a stacked film of Cr/Cu/Ti, C
It is sufficient to butteren r by photo-etching.

次に図(d)の如く、ホトレジストマスクを用いてバン
ブ形成位置においてC「メッキ層に接続するはんだバン
プ7を形成する。ここで、上記ハンダバンプは、例えば
Ni等からなるバンプ下地膜8を介して前記メッキ下地
層上に形成される。
Next, as shown in Figure (d), a photoresist mask is used to form a solder bump 7 that connects to the C' plating layer at the bump forming position. is formed on the plating base layer.

最後に図(e)の如く、Crメッキ層6およびハンダバ
ンプ7をマスクとしてメッキ下地層、即ちCu膜5およ
びTi膜6を選択的にエッチ除去する。
Finally, as shown in Figure (e), the plating base layer, that is, the Cu film 5 and the Ti film 6, is selectively etched away using the Cr plating layer 6 and the solder bumps 7 as masks.

上述の如き本発明の一実施態様によれば、数回のメッキ
処理およびエツチングによる導電層により基板上の任意
の位置にはんだバンプを設けることができ、半導体装置
の小型化、高密度化を容易にすることができる。
According to one embodiment of the present invention as described above, solder bumps can be provided at arbitrary positions on a substrate by using a conductive layer formed by plating and etching several times, making it easy to miniaturize and increase the density of semiconductor devices. It can be done.

また、最上面に形成されたCrメッキ層ははんだに濡れ
ないため、ハンダバンプが基板上に濡れ広がることがな
い。しかも、バンプな基板上に分散して任意の位置形成
しうるため、ボンディングの際の熱による熱疲労等に対
する寿命をのばすことができる。
Further, since the Cr plating layer formed on the top surface does not get wet with solder, the solder bumps do not get wet and spread on the board. Moreover, since they can be dispersed and formed at arbitrary positions on a bumpy substrate, their lifespan against thermal fatigue caused by heat during bonding can be extended.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(e)は本発明の一実施態様を示す工
程毎の集積回路基板の断面図である。 1・・・基板、2・・・配線層、3・・・保護膜、4・
・・Ti膜、5・・・Cu膜、6・・・Crメッキ層、
7・・・バンプ、8・・・バンプ下地層(Ni)。 1”)QJ 第  1  図
FIGS. 1(a) to 1(e) are cross-sectional views of an integrated circuit board at each step, showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring layer, 3... Protective film, 4...
...Ti film, 5...Cu film, 6...Cr plating layer,
7... Bump, 8... Bump base layer (Ni). 1”) QJ Figure 1

Claims (1)

【特許請求の範囲】 1、(a)諸素子の形成された半導体基板と (b)上記半導体基板上に形成された配線層と (c)上記配線層の電極部を除く半導体基板の一主面を
覆う絶縁膜と (d)上記電極部とバンプ形成位置とを接続する上記絶
縁膜上に形成された、一番上の層がハンダに濡れにくい
物質からなる層である、少なくとも2層からなる導電層
と (e)上記バンプ形成位置に設けられたバンプとからな
ることを特徴とする集積回路装置。 2、上記バンプは、その下に必要に応じたバンプ下地層
を持つことを特徴とする特許請求の範囲第1項記載の集
積回路装置。
[Scope of Claims] 1. (a) a semiconductor substrate on which various elements are formed, (b) a wiring layer formed on the semiconductor substrate, and (c) a main body of the semiconductor substrate excluding electrode portions of the wiring layer. (d) an insulating film covering the surface; and (d) at least two layers formed on the insulating film connecting the electrode portion and the bump formation position, the top layer being a layer made of a substance that is difficult to wet with solder. and (e) a bump provided at the bump formation position. 2. The integrated circuit device according to claim 1, wherein the bump has an optional bump underlayer thereunder.
JP60134042A 1985-06-21 1985-06-21 Integrated circuit device Pending JPS6116552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60134042A JPS6116552A (en) 1985-06-21 1985-06-21 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60134042A JPS6116552A (en) 1985-06-21 1985-06-21 Integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3687179A Division JPS55130148A (en) 1979-03-30 1979-03-30 Forming method of bump electrode

Publications (1)

Publication Number Publication Date
JPS6116552A true JPS6116552A (en) 1986-01-24

Family

ID=15119010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60134042A Pending JPS6116552A (en) 1985-06-21 1985-06-21 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6116552A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6392163B1 (en) 1995-04-04 2002-05-21 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6389691B1 (en) 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates

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