JPS6115330A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS6115330A JPS6115330A JP13524584A JP13524584A JPS6115330A JP S6115330 A JPS6115330 A JP S6115330A JP 13524584 A JP13524584 A JP 13524584A JP 13524584 A JP13524584 A JP 13524584A JP S6115330 A JPS6115330 A JP S6115330A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum alloy
- film
- reflectance
- deposited film
- argon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 25
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052786 argon Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000000992 sputter etching Methods 0.000 claims abstract description 11
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 2
- 239000005337 ground glass Substances 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- -1 argon ion Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体集積回路におけるアルミ合金配線を
高精度にできるようにした半導体素子の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor element that enables highly accurate aluminum alloy wiring in a semiconductor integrated circuit.
（従来の技術）
第３図は従来の高反射率のアルミ合金膜を使用した場合
の半導体の集積回路の断面図であシ、この第３図におい
て、ウニ八基板１の上に電極２が形成されておシ、その
上に絶縁膜３を形成し、その上に金属配線となるアルミ
合金膜４を蒸着する。(Prior Art) FIG. 3 is a cross-sectional view of a semiconductor integrated circuit using a conventional high-reflectance aluminum alloy film. In FIG. Once formed, an insulating film 3 is formed thereon, and an aluminum alloy film 4, which will become a metal wiring, is vapor-deposited thereon.
その後、レソスドをコーティングし、ガラスマスク５を
通し、光によシ最終的に得ようとするアルミ合金１ＥＪ
Ｊのレジストパターン６を形成する。After that, the aluminum alloy 1EJ to be finally obtained is coated with resin, passed through a glass mask 5, and exposed to light.
A resist pattern 6 of J is formed.
この場合電極２の部分の断差にしたがって、その上にア
ルミ合金蒸着層にも断差部分が形成される。In this case, in accordance with the difference in the electrode 2 portion, a difference portion is also formed in the aluminum alloy vapor deposited layer thereon.
（発明が解決しようとする問題点）
アルミ合金蒸着膜の反射率が８０チ以上ある場合、断差
の近くにレジストパターン７をガラスマスク５を透過し
た光によって露光形成した場合、近くにある断差のアル
ミ合金面の側面からの反射によシレジストの側面に強い
光が当たるため、レソストがボッタイプであれば、側面
方向からも露光され、最終的に現像されたパターンはレ
ジストパターン７のように細く、りずれたパターンにな
るという欠点、があった。(Problems to be Solved by the Invention) When the reflectance of the aluminum alloy vapor-deposited film is 80 degrees or more, if the resist pattern 7 is formed near the gap by exposure with light transmitted through the glass mask 5, Strong light hits the side of the resist due to reflection from the side of the aluminum alloy surface, so if the resist is a bottom type, it will also be exposed from the side, and the final developed pattern will look like resist pattern 7. The drawback was that the pattern was thin and misaligned.
この発明の目的は、アルミ合金蒸着膜上に精度の高いレ
ジストパターンを形成し、最終的に精度の高いアルミ合
金配線を形成できる半導体素子の製造方法を得ることに
ある。An object of the present invention is to provide a method for manufacturing a semiconductor element that can form a highly accurate resist pattern on an aluminum alloy vapor deposited film and ultimately form highly accurate aluminum alloy wiring.
（問題点を解決するための手段）
この発明の要点は、高反射率のアルミ合金蒸着膜表面を
アルゴン・イオン・スパッタエツチング処理をすること
にある。(Means for Solving the Problems) The gist of the present invention is to perform argon ion sputter etching treatment on the surface of a highly reflective aluminum alloy vapor deposited film.
（作用）
このＡ１合金蒸着膜表面のアルゴンイオンスパッタエツ
チング処理により鏡面であったＡ／蒸着膜表面をスリガ
ラス状にすることができ、低反射率面を得ることができ
る。(Function) By performing the argon ion sputter etching treatment on the surface of the A1 alloy vapor deposited film, the surface of the A/deposited film, which was a mirror surface, can be made into a ground glass state, and a low reflectance surface can be obtained.
（実施例）
以下、この発明の半導体素子の製造方法の実施例につい
て、図面に基づき説明する。第１図はその一実施例の工
程説明図である。この第１図において、第３図と同一部
分には、同一符号を付して述べる。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 1 is a process explanatory diagram of one embodiment. In FIG. 1, the same parts as in FIG. 3 will be described with the same reference numerals.
まず、従来と同様にして、ウェハ基板１の上に電極２を
形成し、その上に絶縁膜３を形成する。First, the electrode 2 is formed on the wafer substrate 1 and the insulating film 3 is formed on it in the same manner as in the conventional method.
この絶縁膜３上に、アルミ合金蒸着膜４を蒸着する。On this insulating film 3, an aluminum alloy deposited film 4 is deposited.
このアルミ合金蒸着膜４を形成する際に、その表面の反
射率を下げるために、ウェハ基板１にスパッタ蒸着装置
でアルミ合金を蒸着した後、そのまま蒸着装置内でアル
ゴンガスを導入してアルゴンスパッタエツチングを行い
、アルミ合雀蒸着膜４の表面をスリガラス状にして反射
率を低下させる。When forming this aluminum alloy vapor deposited film 4, in order to reduce the reflectance of the surface, after the aluminum alloy is vapor deposited on the wafer substrate 1 using a sputter vapor deposition apparatus, argon gas is directly introduced into the vapor deposition apparatus and argon sputtering is performed. Etching is performed to make the surface of the aluminum alloy vapor-deposited film 4 ground glass-like and reduce the reflectance.
このように、アルミ合金蒸着膜４の表面をアルゴンスパ
ッタエツチング処理を行う。この処理を行えば周知のよ
うに、アルゴンイオンがアルミ表面をたたくので、その
表面がスリガラス状（ざらざら）になる。したがってア
ルミ表面の反射率が低下する。In this manner, the surface of the aluminum alloy vapor deposited film 4 is subjected to argon sputter etching treatment. As is well known, when this treatment is performed, argon ions strike the aluminum surface, making the surface rough. Therefore, the reflectance of the aluminum surface decreases.
前述したように、この処理はスパッタ蒸着装置内で連続
して行えるので工程上も簡単である。その後、レソスト
をコーティングし、ガラスマスク５を通して露光する。As mentioned above, this process can be performed continuously in a sputter deposition apparatus, so the process is simple. Thereafter, the resist is coated and exposed through a glass mask 5.
この場合、断差の近くにあるレジストパターン７も断差
側面からの２次反射が大巾に弱くなゐため、高精度のレ
ジストパターンを得ることができる。In this case, the secondary reflection from the side surfaces of the difference is also greatly weakened in the resist pattern 7 near the difference, so that a highly accurate resist pattern can be obtained.
ｉ２図にアルゴン・スパッタエツチング時間に対、する
ＡＬ−８ｉ合金の表面反射率を示す。横軸はアルゴン・
イオン・スパッタエツチング時間、縦軸にＡＬ−８ｔ合
金の表面反射率を示す。蒸着を行なったままのＡＬ−８
ｉ合金の表面反射率は９０％以上を示すが、アルゴン・
イオン・スパッタエツチング時間が長くなるにしたがっ
て低下する。Figure i2 shows the surface reflectance of the AL-8i alloy versus the argon sputter etching time. The horizontal axis is argon.
The ion sputter etching time and the vertical axis indicate the surface reflectance of AL-8t alloy. AL-8 as-deposited
The surface reflectance of i-alloy is over 90%, but argon
It decreases as the ion sputter etching time increases.
ただし、ある時間よシ長くなった場合、反射率の低下は
ほぼ止まシ、一定値とな夛、それ以上行う必要はない。However, if the time is longer than a certain time, the decrease in reflectance will almost stop and will remain at a constant value, so there is no need to do anything further.
実駁髭果から反射率は６０％以下であれば、良好なレジ
ストパターンを形成できる。As long as the reflectance is 60% or less, a good resist pattern can be formed.
（発明の効果）
この発明は以上説明したように、反射率の高いアルミ合
金ｓｋｉ表面をアルゴンイオンエツチング処理によシ低
反射率化するようにしたので、アルミ合金点Ｎ膜上に高
精度のレジストパターンを形成できるという利点がある
。(Effects of the Invention) As explained above, this invention reduces the reflectance of the aluminum alloy ski surface with high reflectance by argon ion etching treatment. It has the advantage that a resist pattern can be formed.
さらに、アルミ合金膜蒸着装置内で連続的に行うことが
できるため、きわめて簡単に行な゛え、他の高反射率膜
上のレジストパターン形成に利用できる。Furthermore, since it can be performed continuously in an aluminum alloy film deposition apparatus, it is extremely easy to perform and can be used for forming resist patterns on other high reflectance films.
第１図はこの発明の半導体素子の製造方法の一実施例の
工程説明図、第２図は同上半導体素子の製造方法を説明
するためのアルゴンスパッタエツチング時間に対するＡ
Ｌ−８ｔ合金の表面反射率を示す図、第３図は従来の半
導体集積回路の断面図である。
１・・・ウェハ基板、２・・・電極、３・・・絶縁膜、
４・・・アルミ合金蒸着膜、５・・・ガラスマスク、６
．・７・・・レジストパターン。
特許出願人 沖電気工業株式会社
第１図
一アルコノイオノ・スノー、タエー、＋ング日ｉＭ第３
図FIG. 1 is a process explanatory diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is an illustration of A versus argon sputter etching time for explaining the method for manufacturing the same semiconductor device.
FIG. 3, which is a diagram showing the surface reflectance of L-8t alloy, is a cross-sectional view of a conventional semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Wafer substrate, 2... Electrode, 3... Insulating film,
4... Aluminum alloy vapor deposited film, 5... Glass mask, 6
．．・7...Resist pattern. Patent Applicant Oki Electric Industry Co., Ltd. Figure 1 Alcono Iono Snow, Tae, + Ng Day iM No. 3
figure
Claims (1)
アルミ合金をスパッタ蒸着装置で蒸着してアルミ合金蒸
着膜を形成するとともに、このスパッタ蒸着装置内で連
続的にアルゴンスパツタエツチング処理を行う行程と、
このアルミ合金蒸着膜上にレジストパターンを形成する
工程を含むことを特徴とする半導体素子の製造方法。In a semiconductor integrated circuit having aluminum alloy wiring, a step of depositing the aluminum alloy using a sputter deposition device to form an aluminum alloy deposited film, and continuously performing an argon sputter etching process in the sputter deposition device;
A method for manufacturing a semiconductor device, comprising the step of forming a resist pattern on the aluminum alloy vapor deposited film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13524584A JPS6115330A (en) | 1984-07-02 | 1984-07-02 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13524584A JPS6115330A (en) | 1984-07-02 | 1984-07-02 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115330A true JPS6115330A (en) | 1986-01-23 |
Family
ID=15147198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13524584A Pending JPS6115330A (en) | 1984-07-02 | 1984-07-02 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115330A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933304A (en) * | 1988-11-03 | 1990-06-12 | Sgs-Thomson Microelectronics, Inc. | Method for reducing the surface reflectance of a metal layer during semiconductor processing |
| US4992152A (en) * | 1989-04-20 | 1991-02-12 | Eastman Kodak Company | Reducing hillocking in aluminum layers formed on substrates |
| EP0495755B2 (en) † | 1991-01-11 | 2001-12-19 | Alcan Technology & Management AG | Aluminium rolled products |
-
1984
- 1984-07-02 JP JP13524584A patent/JPS6115330A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933304A (en) * | 1988-11-03 | 1990-06-12 | Sgs-Thomson Microelectronics, Inc. | Method for reducing the surface reflectance of a metal layer during semiconductor processing |
| US4992152A (en) * | 1989-04-20 | 1991-02-12 | Eastman Kodak Company | Reducing hillocking in aluminum layers formed on substrates |
| EP0495755B2 (en) † | 1991-01-11 | 2001-12-19 | Alcan Technology & Management AG | Aluminium rolled products |
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