JPS61139856A - Data processor - Google Patents

Abstract

PURPOSE:To improve availability without adding any special circuit by reading a correct storage key out of an address of another main memory corresponding to the address of wrong data when a fixed read data error occurs, and correcting it. CONSTITUTION:When a central processor 3 refers to, for example, an address #8 of a main memory, a request to refer is sent to the 2nd main memory 2 to refer to data in the address #8 of the 2nd main memory 2 and also read a storage key out of a key memory 22, thereby making a check on the protection of the reference. At this time, a data error occurs in the read data from the key memory 22, the referring of data is interrupted and this data error is reported to the central processor 3 by a control circuit 23. The central processor 3 when detecting the read data error of the key memory 22 sends the corresponding address of the key memory 22 stored with the wrong data to the 1st main memory 1 to read a correct storage key, and corrects the 2nd main memory 2 to carry on the request to refer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more particularly to modification of a storage key that controls access to a main storage section.

[Conventional technology]

The data processing device includes a main memory unit, multiple main memory units such as key memories for controlling access to the main memory unit, and a central processing unit to which these main memory units are connected via a common bus. Please note that the device is equipped with the following. With this data processing lid, even if a data error occurs when reading from the key memory, if it is an instantaneous error, it can be recovered by retrying the read. However, if this data error is a fixed error, it cannot be recovered even by retrying reading, so data processing cannot be continued.
ability) is significantly reduced.

Conventionally, this unrecoverable fixed error has been dealt with by adding a 1-bit error correction code to the key memory.

[Problem that the invention seeks to solve]

In the conventional data processing device as described above, adding a 1-bit error correction code requires adding a considerable amount of circuitry for verification, making the device complicated;
The problem is that it leads to higher costs.

The present invention has been made to solve these problems, and an object of the present invention is to provide a data processing lid with a simple configuration that does not require the addition of a special circuit for correcting data errors.

[Means for solving problems]

In the data processing device according to the present invention, when a data error occurs in the key memory of any one of a plurality of main storage devices, the other main storage device corresponding to the address of the erroneous data is The central processing unit is provided with a memory key reading function for reading a memory key from an address and a memory key storage function for storing the read memory key in the key memory of the main memory where the error occurred.

[Effect]

In this invention, when a fixed read data error occurs, a correct memory key is extracted from the address of another main memory device corresponding to the address of the error data, and this memory key is used to generate the error. It attempts to correct it by storing it in the key memory of the main storage and continue processing.

〔Example〕

The first factor is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the connection state of this embodiment.

In FIGS. 1 and 2, (1) is the first main memory! In the main memory section (2), a key memo that stores the memory keys that control access to this main memory section, these main memory sections and the key memory (control circuit Q11 that controls the increase) are stored. (2) is the first main memory (
A main memory unit (8) has a main memory unit (21), a key memo IJE, and a control circuit similar to that of 1), and (8) is a central processing unit, which executes the microprogram (5a) and stores the above-mentioned key memo IJ (12). , H's storage key reading function (31), storage (2), and central processing unit (8).

By the way, these two main memories (1) and (2) are assumed to be interleaved every 8 bytes (double word boundary), and the key memory (to) and @@ are interleaved every 4 kilobytes of main memory data. Assume that each has one value and each holds exactly the same content. Further, it is assumed that even-numbered double words are allocated to the first main storage device (1), and odd-numbered double words Fi are allocated to the second main storage device (2).

The operation of the data processing apparatus configured as described above will be described below.

First, when the central processing unit (3) refers to address 8 of the main memory, the reference request is sent to the second main memory (2).
)K is issued, and in this second main memory (2), along with the reference to the data at address 8, the storage key of ) is read out into the key memory and checked for protection of the reference. At this time,
When a data error occurs in the read data of the key memory (a), data reference is interrupted and this data error is reported to the central processing unit (8) by the control circuit.

Next, when the central processing unit (3) detects an error in the read data of the key memory (2), it sends the corresponding address of the key memory (2) that stores the erroneous data to the first storage device (1). , read out the correct memory key.

The correct storage key read out in this way is sent to the second main storage device (2)K with an error generated and stored at the corresponding address in the key memory (4).

Thereafter, the central processing unit (8) issues a reference request for address 8 again to continue the process. These operations are performed by a microprogram (3a) having a memory key reading function group) and a memory key storage function.

Thus, when a fixed read data error occurs in the key memory in either main memory, the incorrect data can be corrected using the correct content in the same yellow position in the key memory in the other main memory. processing can continue.

Note that in the above embodiment, two main storage devices and a central processing unit are connected on the same bus.
Even in a data processing device in which three or more main storage devices are connected in the same way, the same operation as described above can be performed.

〔Effect of the invention〕

As explained above, the present invention uses a microprogram in the central processing unit to correct data errors in the key memory of any main storage device with correct data in the key memory of another main storage device. , there is no need to add special circuits to correct fixed data errors, it is possible to configure an easy-to-use and low-cost data processing device, and the availability of the device can be easily improved. There is.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of this invention, and Fig. 2 is a circuit diagram showing the connection state of this embodiment. Device (3a)...Microprogram (4)Fist/Data bus αNO+ (2tl...Main memory shout, Yanobu O key memory (13), Lord)...Control circuit, (811/Nake memory key readout Function: Memory key storage function Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A main memory section, a key memory storing a memory key for controlling access to the main memory section, a plurality of main memory devices each having a control circuit for controlling the key memory and the main memory section, and these main memories. In a data processing device, the device is provided with a central processing unit connected via a common bus, the content of the key memory of the main storage device is the same, and the data processing device operates interleaved in units of predetermined blocks. The processing device has a memory key reading function that reads out a correct memory key from an address of another main memory corresponding to the address of the error data in response to an error in read data of the key memory in any one of the main memory devices; A data processing device comprising a storage key storage function for storing a correct storage key issued in the key memory of the main storage device in which the error occurred.