JPS61126680A - Address buffer for cmos memory - Google Patents

Abstract

PURPOSE:To output an internal address signal at a high speed without causing a malfunction by making a pre part output signal into three states at the time of stand-by and at the time of an action. CONSTITUTION:At the time of the stand-by, an address control signal -phi is H, phiL and phiS are L, a point N11 and pre part output signals phii and -phii are L and points N12-N16 go to be H. At the time of an action, -phiS is from H to L, when an external address signal phiAD is H, -phiS is from H to L, a Q22 is off, a Q24 is on, and a point N11 is L and a Q21 goes to be on. Next, when phiS is from L to H, through an FF13 a point N14 is L, a point N15 is H and the signal phii goes to be L. On the other hand, the signal phiAD is L, and when -approx.=S is from H to L, a point N11 is from L to H, a Q26 is on, the signal phii is H and -phii goes to be L. The signal phiL raises phiS, and thereafter, the signal raises up to a high electric potential in order to latch the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address buffer for 0MO8 (complementary tpiMO8) memory.

A circuit diagram showing the configuration of an example, and FIG. 4 is an operation timing chart thereof.

In FIG. 3, 1 is a pre-part, and 2 is a main part. In the pre-part 1 and the main part 2 shown in FIG. 3, the standby state occurs at the nodes Nl, N3 . N4 is at a high potential and node N2 is at a low potential. The operation starts when the address control signal φP becomes high potential, and the P channel M
O8) The process begins by turning off transistor (hereinafter referred to as PchTr) Q8. Next, address control signal φ
With S becoming a high potential, PchTr Ql = Q2
, and N-channel MO8) transistor (hereinafter referred to as NchTr
That's what it means. )Q3. PchT of NAND circuit consisting of Q4
rQ2 is turned off and NchTrQ4 is turned on.

At this time, if the external input address signal φD is at a high potential, the Pch Tr Q1 is turned off and the Nch TrQ3 is turned on, so that the node N1 is drained from the high potential to the low potential. Therefore, at node N2 after one stage of inverter, PchTrQ5 is on and NchTrQ6 is on.
By turning off, the potential changes from low to high.

At this time, Nch TrQ7 is also in the on state at the same time, but since the Nch TrQ6 is in the off state, there is no difference from the node N3 to the standby state, and the pre-part output signal φi is at a low potential and φi is at a high potential. It remains as it is.

Conversely, if the external address signal φmD is at the potential, Pc
Since the h Tr Q 1 is on and the Nch Tr Q 3 is off, the node N1 is at a high potential and the node N2 is at a low potential as in the standby state. However, Nch Tr
Since Q7 is turned on, node N3 becomes Nch
Charge is extracted from high potential to low potential through Tr Q7 and Q6. Therefore, the pre-part output signal φi
changes from a low potential to a high potential, and φi changes from a high potential to a low potential.

As mentioned above, the combination of the pre-part output signals φi and φi is
Since there are only two states where one of them is at a low potential and the other is at a high potential, it is necessary in the main section 2 to further establish a logic with the address drive signal φE. That is, Pch Tr Q 13 eQ14 and Nch Tr
This is the NAND circuit consisting of Ql 5 and Ql 6, F'ch Tr Q 13 and Nch Tr
The pre-part output signal φi or φi of the signal entering the gate of Q15 becomes high potential and turns off the Pch Tr Q13.

After turning on the Nch Tr Q 15, the address drive signal φB goes to a high potential state, so that the node N4 goes from a high potential to a low potential, and the Pch Tr Q 17 eN
An inverter consisting of ch Tr Q 18 outputs an internal address signal φ0.

Since the pre-part output signals φi and φi have only two states, there is a problem in determining the timing for setting the address drive signal φE to a high potential in the main part 2.

That is, when the external input address signal φAD is at a low potential, when the operation starts, the pre-part output signal φi changes from a high potential to a low potential, but before the Pch Tr Ql3 is in the off state and the Nch Tr Q15 is in the off state. When the address drive signal φE becomes high potential, the Nch Tr Q
16 is turned on, the potential of the node N4, which has been charged to a high potential, is removed. If the potential drops to a level that turns on the Pch TrQ17 of the inverter at the next stage, a malfunction will occur in which the internal address signal φ0, which should not originally be selected, is output.

Therefore, in order to operate the address buffer stably, it is necessary to wait for the rise of the address drive signal φE until the potentials of the pre-part output signals φi and φi have fallen firmly to a high or low potential. For this reason, an address buffer having a dual output signal in its pre-circuit section, like the conventional address buffer, has the problem that speeding up is limited by the input of the drive signal.

Therefore, an object of the present invention is to solve the problems of the conventional technology as described above, thereby providing a CM that operates at high speed and stability.
The purpose is to provide an address buffer for OS memory.

[Means for solving problems]

The CMOS memory address buffer of the present invention includes a first P-channel transistor whose gate is connected to an external input address signal, whose source is connected to a power supply, and whose drain is connected to a second node, and whose inputs are connected to the external address input signal and the first P-channel transistor. a NOR circuit whose output is connected to the first node, a second P-channel transistor whose gate is connected to the first node, whose source is connected to the power supply, and whose drain is connected to the third node. , a third P-channel transistor having a gate connected to the second address control signal, a source connected to the second node, a drain connected to the fourth node, and a gate connected to the second address control signal, a source connected to the a fourth P-channel transistor whose drains are respectively connected to the fifth node at the M30 node; a fifth P-channel transistor whose drains are respectively connected to the fourth node; a first N-channel transistor whose drains are respectively connected to the fourth node; a flip-flop circuit consisting of a 60th P-channel transistor and a second N-channel transistor connected to the fifth node, respectively; a gate is connected to a third address control signal; a drain is common to the sources of the first and second ON-channel transistors; a third N-channel transistor whose source is connected to the ground point at the node; and a 70th P-channel transistor whose gate is connected to the third address control signal, whose source is connected to the power supply, and whose drain is connected to the fourth node. an eighth P-channel transistor having a gate connected to the third address control signal, a source power supply, and a drain connected to the fifth node; and a first pre-channel transistor having an input connected to the fourth node. a first inverter that outputs an output signal; a second inverter having an input connected to the fifth node and outputting a second pre-unit output signal; a main part consisting of a third inverter whose output is connected to the sixth node, and a fourth inverter whose input is connected to the sixth node and outputs an internal address signal. have.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an operation timing chart thereof.

In this embodiment, a first Pch Tr Q21 whose gate is connected to the external input address signal φD, whose source is connected to the power supply VDD, and whose drain is connected to the second node N12, and whose input is connected to the external address input signal φAD and the first P whose outputs are connected to the address control signal φS and the first node Nil, respectively.
chTrQ22. Q23 and Nch Tr Q24,
A NOR circuit consisting of Q25, the gate is the node Nil, the source is the current rJAvDD, and the drain is the third node NL3
W for each! Continued 20th E'ch Tr Q 2
6 and a third PchTrQ27 whose gate is connected to the second address control signal φL and whose source is connected to the node N12 and whose drain is connected to the fourth node N14, whose gate is connected to the address control signal φL and whose source is connected to the node N13. is the fifth
The fourth Pch Tr connected to the node N15 of
Q Z 8, a fifth Pch Tr Q29 and a first Nch T whose drains are respectively connected to the node N14.
r Q 31 and a sixth Pch Tr Q 30 and a second Nch whose drains are respectively connected to the node N15.
A flip-flop circuit 13 consisting of Tr Q 32;
The gate applies the drain force Nc to the third address control signal φS.
h Tr Q 31 .

A third Nch Tr Q33 whose source is connected to the common source contact of Q32 and the ground point, and a seventh Pch Tr whose gate is connected to the address control signal φS, whose source is connected to the power supply VDD, and whose drain is connected to the node N141, respectively.
Q 34, an eighth Pch Tr Q 35 whose gate is connected to the address control signal φS, whose source is connected to the power supply VDD, and whose drain is connected to the node N15, and whose input is connected to the node N1.
5 and outputs the first pre-part output signal φi,
A first inverter consisting of a channel Tr Q38 and an Nch Tr Q39 has an input connected to a node N14 and outputs a second pre-part output signal φi, or a sixth inverter has an output connected to the second pre-part output signal φi and φi. F'ch Tr Q40°Nch Tr Q connected to node N16 of
E'ch T whose input is connected to node N16 and outputs internal address signal φ0.
r Q42 and a fourth inverter consisting of an Nch Tr Q43.

Next, the operation of this embodiment will be explained with reference to the operation timing chart of FIG.

As shown on the right in FIG. 1, in the standby state, the address control signal φS is at a high potential, and the address control signal φS is at a low potential.
Node NIL and pre-part output signal φin l' t are at low potential, and node N12. N13. N14°N15. N16 is at a high potential.

The operation begins when the address image signal φS changes from a high potential to a low potential. When the external address signal φD is at a high potential, the address control signal φS changes from a high potential to a low potential, so that the PchTrQ22 is turned off.
NcklTr Q 24 is in the on state, and the potential of the node Nil is at a low potential as in the standby state. Therefore, P
When the gate potentials of channels Q21 and Q26 are set to VG(Q21) and VG(Q26)-, respectively, VG(Q21)>VaCQ26). 1
c7) By raising the response control signal φS from a low potential to a high potential, the s Pch Tr Q 34 = Q 35 is turned off, and the Nch Tr is turned off while stopping the current supply from the 11E source VDD, but VG (Q21)>VG(
Q26) Current I flowing through PchTrQ21
on (Q21) and tfflt Ion (Q26 on) flowing through PchTr Q26.
) < fan (Q26), so it's fake.

is on state B e E'ch 'rr Q29 s Nc
h Tr Q32 is turned off, node N14 remains at low potential and node N15 remains at high potential. Therefore F'ch
Although the pre-section output signal φi changes from a low potential to a high potential by an inverter consisting of Tr Q36 and Nch Tr Q37, the pre-section output signal φi remains at a low potential because the node N15 remains at a high potential.

Conversely, when external input address signal φAD is at a low potential, P
ch Tr Q22 is on, Nch Tr Q24
Since the address control signal φS changes from high potential to low potential, PchTr Q23 is turned on, Nch Tr Q25 is turned off, and the node Nil
change from low potential to high potential. Therefore, next time HaVaCQ
21) <Ve(Q26) Theal o Hereafter o
1th key is the same as when the external input address signal φ is at a high potential, but Ion (Q21)>Ion
(Q26) Therefore, the node N15 is pulled to a low potential while the node N14 remains at a high potential. Therefore, Pch
Tr Q38.

The pre-part output signal φi changes from a low potential to a high potential by an inverter consisting of an Nch Tr Q 39, and φi remains at a low potential.

After raising the address control signal φS, the address control signal φL is raised to a higher potential in order to latch data.

〔Effect of the invention〕

As explained above in detail, the uninvented address buffer for CMOS memory uses the above means to have its pre-part output signals φi, φi both at a low potential during standby, and one of them becomes a high potential during operation. Since it takes the form of 3 states, unlike the conventional address buffer which takes the form of 2 states, there is no need to further input the address drive signal after exiting the pre-circuit, so it is possible to avoid malfunctions as in the case of the conventional address buffer. The internal address signal can be output at high speed simply by pressing the inverter as shown in the main part of Fig. 1.

Therefore, according to the present invention, a CM that operates at high speed and stably
An address buffer for OS memory is obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, a circuit diagram showing its construction, and FIG. 4 is an operation timing chart thereof. Q27. Q28. Q29. Q30. Q34. Q35. Q
36. Q3B. Q10. Q42...--1' channel 1vlOS transistor, Q24. See 25. Q31. Q32. Q33.
Q37. Q39. Q41゜Q43...N-channel MOS transistor, vDD...Power supply, φED...-External manual address signal, φ89. . ...address drive signal, φi, φi...pre-member signal, φsIφS...address control signal, φ0...internal address signal.

Claims (1)

[Claims] a first P-channel transistor having a gate connected to an external input address signal, a source connected to a power supply, and a drain connected to a second node; an input connected to the external address input signal and a first address control signal; a NOR circuit connected to each node, a second P-channel transistor having a gate connected to the first node, a source connected to the power supply, a drain connected to the third node, and a gate connected to the second address control signal. a third P-channel transistor having a source connected to the second node, a drain connected to the fourth node, a gate connected to the second address control signal, a source connected to the third node, and a drain connected to the fifth node; a fourth P-channel transistor each connected to the node; a fifth P-channel transistor and a first N-channel transistor each having a drain connected to the fourth node; and a first N-channel transistor, each having a drain connected to the fifth node. a flip-flop circuit having a gate connected to a third address control signal and a drain connected to a common connection point between the sources of the first and second N-channel transistors; a third N-channel transistor whose gate is connected to the ground point, and a seventh N-channel transistor whose gate is connected to the third address control signal, whose source is connected to the power supply, and whose drain is connected to the fourth node, respectively.
an eighth P-channel transistor whose gate is connected to the third address control signal, whose source is connected to the power supply, and whose drain is connected to the fifth node, and whose input is connected to the fourth node. a first inverter that outputs a first output signal; a second inverter having an input connected to the fifth node and outputting a second output signal; a third inverter whose output is connected to the sixth node for the first or second pre-part output signal, and a fourth inverter whose input is connected to the sixth node and outputs an internal address signal. A CMO characterized by comprising a main part
Address buffer for S memory.