JPS6112635Y2 - - Google Patents
Info
- Publication number
- JPS6112635Y2 JPS6112635Y2 JP16733281U JP16733281U JPS6112635Y2 JP S6112635 Y2 JPS6112635 Y2 JP S6112635Y2 JP 16733281 U JP16733281 U JP 16733281U JP 16733281 U JP16733281 U JP 16733281U JP S6112635 Y2 JPS6112635 Y2 JP S6112635Y2
- Authority
- JP
- Japan
- Prior art keywords
- data
- prom
- circuit
- data holding
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012790 confirmation Methods 0.000 claims description 8
- 230000014759 maintenance of location Effects 0.000 claims description 6
- 238000013524 data verification Methods 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 101000610551 Homo sapiens Prominin-1 Proteins 0.000 description 1
- 102100040120 Prominin-1 Human genes 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
【考案の詳細な説明】
本考案はPROMの書込み確認装置に関するもの
である。[Detailed Description of the Invention] The present invention relates to a PROM write confirmation device.
従来PROM書込み確認装置はPROMにアドレス
信号とチツプセレクト信号をあたえ、前記PROM
から出力されるデータを書込みデータと照合して
確認していたが、照合するまでに前記PROMのア
クセス時間以上必要とするため、前記アクセス時
間の不良のPROMについてはPROM書込み確認装
置では良品と判断される欠点があつた。 Conventional PROM writing confirmation devices give address signals and chip select signals to the PROM, and
The data output from the was verified by comparing it with the written data, but since it takes longer than the access time of the PROM to perform the comparison, the PROM writing confirmation device judges that the PROM with a defective access time is good. There were some drawbacks.
本考案の目的は、上記の欠点を除去するために
PROM書込み確認の際にPROMにあたえるアドレ
ス信号とチツプセレクト信号とから前記PROMの
アクセス時間だけ遅延されたデータ保持パルスを
発生させるデータ保持パルス発生回路と前記
PROMからのデータを前記データ保持パルスのタ
イミングに保持するデータ保持回路と前記データ
保持回路の出力と書込みデータを照合するデータ
照合回路とにより前記PROMのアクセス時間が規
格内であるか確認することを可能としたPROM書
込み確認装置を提供することにある。 The purpose of this invention is to eliminate the above drawbacks.
a data retention pulse generation circuit that generates a data retention pulse delayed by the access time of the PROM from the address signal and chip select signal applied to the PROM at the time of PROM write confirmation;
A data holding circuit that holds data from the PROM at the timing of the data holding pulse and a data verification circuit that checks the output of the data holding circuit and the written data confirm whether the access time of the PROM is within the standard. The purpose of the present invention is to provide a PROM writing confirmation device that enables writing.
図は本考案の一実施例を示し、１はPROM、２
はアドレス信号、３はチツプセレクト信号、４は
出力データ、５はデータ保持パルス発生回路、６
はデータ保持パルス、７はデータ保持回路、８は
照合データ、９はデータ照合回路、１０は書込み
データ、１１は判定データである。この図におい
てPROM１は書込み確認の際、アドレス信号２と
チツプセレクト信号３により出力データ４を発生
すると共にデータ保持パルス発生回路５は前記チ
ツプセレクト信号３により前記PROM１のアクセ
ス時間遅延されたデータ保持パルス６を発生す
る。データ保持回路７は前記データ保持パルス６
のタイミングで前記PROM１からの出力データ４
を保持し照合データ８を出力してデータ照合回路
９は前記照合データ８と書込みデータ１０とを照
合して判定データ１１を出力する。 The figure shows one embodiment of the present invention, 1 is PROM, 2
is an address signal, 3 is a chip select signal, 4 is output data, 5 is a data holding pulse generation circuit, 6
is a data holding pulse, 7 is a data holding circuit, 8 is verification data, 9 is a data verification circuit, 10 is write data, and 11 is judgment data. In this figure, PROM 1 generates output data 4 in response to address signal 2 and chip select signal 3 during write confirmation, and data retention pulse generation circuit 5 generates a data retention pulse delayed by the access time of PROM 1 in response to chip select signal 3. Generates 6. The data holding circuit 7 has the data holding pulse 6
Output data 4 from PROM1 at the timing of
The data collation circuit 9 collates the collation data 8 with the write data 10 and outputs the determination data 11.
上記の動作により前記PROM１のアクセス時間
が規格以上の場合、前記データ保持回路７には書
込みデータ１０と異なるデータが保持され、デー
タ照合回路９は、不良の判定データ１１を出力し
アクセス時間の不良のPROMをPROM書込み確認
の際に検出でき、PROMを使用する装置の調整検
査が効率より行うことが可能となる。 If the access time of the PROM 1 exceeds the standard due to the above operation, data different from the write data 10 is held in the data holding circuit 7, and the data collation circuit 9 outputs defect judgment data 11, indicating that the access time is defective. PROM can be detected during PROM writing confirmation, making it possible to perform adjustment inspection of devices using PROM more efficiently.
図は本考案の一実施例を示すブロツク図で、１
はPROM、２はアドレス信号、３はチツプセレク
ト信号、４は出力データ、５はデータ保持パルス
発出回路、６はデータ保持パルス、７はデータ保
持回路、８は照合データ、９はデータ照合回路、
１０は書込みデータ、１１は判定データである。
The figure is a block diagram showing one embodiment of the present invention.
is a PROM, 2 is an address signal, 3 is a chip select signal, 4 is output data, 5 is a data holding pulse generation circuit, 6 is a data holding pulse, 7 is a data holding circuit, 8 is verification data, 9 is a data verification circuit,
10 is write data, and 11 is judgment data.
Claims (1)
レス信号とチツプセレクト信号とから前記PROM
のアクセス時間だけ遅延されたデータ保持パルス
を発生させるデータ保持パルス発生回路と前記
PROMからのデータを前記データ保持パルスのタ
イミングに保持するデータ保持回路と前記データ
保持回路の出力と書込みデータを照合するデータ
照合回路とにより構成されることを特徴とする
PROM書込み確認装置 The PROM is selected from the address signal and chip select signal applied to the PROM when confirming PROM writing.
a data retention pulse generation circuit that generates a data retention pulse delayed by an access time of
The device is characterized by being comprised of a data holding circuit that holds data from the PROM at the timing of the data holding pulse, and a data verification circuit that checks the output of the data holding circuit and the written data.
PROM write confirmation device
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16733281U JPS5872798U (en) | 1981-11-10 | 1981-11-10 | PROM writing confirmation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16733281U JPS5872798U (en) | 1981-11-10 | 1981-11-10 | PROM writing confirmation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5872798U JPS5872798U (en) | 1983-05-17 |
| JPS6112635Y2 true JPS6112635Y2 (en) | 1986-04-19 |
Family
ID=29959432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16733281U Granted JPS5872798U (en) | 1981-11-10 | 1981-11-10 | PROM writing confirmation device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5872798U (en) |
-
1981
- 1981-11-10 JP JP16733281U patent/JPS5872798U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5872798U (en) | 1983-05-17 |
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