JPS61124110U - - Google Patents

Info

Publication number
JPS61124110U
JPS61124110U JP857085U JP857085U JPS61124110U JP S61124110 U JPS61124110 U JP S61124110U JP 857085 U JP857085 U JP 857085U JP 857085 U JP857085 U JP 857085U JP S61124110 U JPS61124110 U JP S61124110U
Authority
JP
Japan
Prior art keywords
output
detector
calibration signal
certain period
muting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP857085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP857085U priority Critical patent/JPS61124110U/ja
Publication of JPS61124110U publication Critical patent/JPS61124110U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Noise Elimination (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロツク図、
第2図は従来例のブロツク図である。 1…フロントエンド、2…IF検波器、3…M
PX部、4…ミユーテイング回路、5…検出器、
6…出力端、7…入力端、8…発振器、9…スイ
ツチ、10…受信機、11…他機器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram of a conventional example. 1...Front end, 2...IF detector, 3...M
PX section, 4... Muting circuit, 5... Detector,
6... Output end, 7... Input end, 8... Oscillator, 9... Switch, 10... Receiver, 11... Other equipment.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源のオン状態を検出する検出器と、検出器の
出力によつて一定時間出力を減衰させるミユーテ
イング回路と、ミユーテイング回路の動作時、一
定時間、上記検出器の出力によつて較正信号を出
力する発振器とを具備したことを特徴とする較正
信号出力装置。
a detector that detects the on state of the power supply; a muting circuit that attenuates the output for a certain period of time according to the output of the detector; and a calibration signal that outputs a calibration signal using the output of the detector for a certain period of time when the muting circuit is in operation. A calibration signal output device characterized by comprising an oscillator.
JP857085U 1985-01-23 1985-01-23 Pending JPS61124110U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP857085U JPS61124110U (en) 1985-01-23 1985-01-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP857085U JPS61124110U (en) 1985-01-23 1985-01-23

Publications (1)

Publication Number Publication Date
JPS61124110U true JPS61124110U (en) 1986-08-05

Family

ID=30487980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP857085U Pending JPS61124110U (en) 1985-01-23 1985-01-23

Country Status (1)

Country Link
JP (1) JPS61124110U (en)

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