JPS6112385B2 - - Google Patents

Info

Publication number
JPS6112385B2
JPS6112385B2 JP52154821A JP15482177A JPS6112385B2 JP S6112385 B2 JPS6112385 B2 JP S6112385B2 JP 52154821 A JP52154821 A JP 52154821A JP 15482177 A JP15482177 A JP 15482177A JP S6112385 B2 JPS6112385 B2 JP S6112385B2
Authority
JP
Japan
Prior art keywords
semiconductor device
solder
semiconductor
semi
solder paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52154821A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5486275A (en
Inventor
Eikichi Wakamatsu
Tomoichi Oku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15482177A priority Critical patent/JPS5486275A/ja
Publication of JPS5486275A publication Critical patent/JPS5486275A/ja
Publication of JPS6112385B2 publication Critical patent/JPS6112385B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP15482177A 1977-12-21 1977-12-21 Manufacture of semiconductor Granted JPS5486275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15482177A JPS5486275A (en) 1977-12-21 1977-12-21 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15482177A JPS5486275A (en) 1977-12-21 1977-12-21 Manufacture of semiconductor

Publications (2)

Publication Number Publication Date
JPS5486275A JPS5486275A (en) 1979-07-09
JPS6112385B2 true JPS6112385B2 (de) 1986-04-08

Family

ID=15592600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15482177A Granted JPS5486275A (en) 1977-12-21 1977-12-21 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS5486275A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267355A (ja) * 1985-05-21 1986-11-26 Fuji Plant Kogyo Kk 半導体パツケ−ジ組立工程での外装処理方法
JPS63142841A (ja) * 1986-12-05 1988-06-15 Fuji Plant Kogyo Kk リ−ドフレ−ムへの半田外装処理方法
JPS63148669A (ja) * 1986-12-12 1988-06-21 Fuji Plant Kogyo Kk リ−ドフレ−ムへの半田外装方法

Also Published As

Publication number Publication date
JPS5486275A (en) 1979-07-09

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